Event time-stamping

• US 20050091554A1
• Filed: 08/07/2003
• Published: 04/28/2005
• Est. Priority Date: 08/07/2003
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Loukianov, Dmitrii
• Application Number:
  US10/637,301
• Publication Number:
  US 20050091554A1
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock

Abstract

Machine-readable media, methods, and apparatus that time stamp events. In one embodiment, a time-stamping circuit may detect events of interest such as interrupt signals, arbitration signals, etc. In response to detecting such an event, the time-stamping circuit may store a time stamp for the event. A requester such as a processor may later request the time-stamping circuit for the time stamp of the event. The requester may then adjust a processing rate associated with the generation of such events based upon the retrieved time stamps.

Claims

1. A method comprising

detecting an event with an apparatus,

stamping the event with a time stamp of the apparatus in response to detecting the event,

receiving a request for the time stamp of the event, and

providing the time stamp for the event in response to receiving the request.

2. The method of claim 1 further comprising

determining whether the event is to be time stamped, and

stamping the event with the time stamp in response to determining that the event is to be time stamped.

3. The method of claim 1 wherein detecting the event comprises detecting an arbitration grant.

4. The method of claim 1 wherein detecting the event comprises detecting an interrupt.

5. The method of claim 1 further comprising adjusting a processing rate of the stream based upon the time stamp for the event and a time stamp of a stream.

6. The method of claim 1 further comprising re-sampling a stream based upon the time stamp for the event and a time stamp of the stream.

7. An apparatus comprising

a counter to update a count in response to a reference clock,

a controller to detect events and to provide detected events with time stamps that are based upon the count of the counter, and

an interface to output the time stamp of a detected event in response to receiving a request for the detected event.

8. The apparatus of claim 7 further comprising an event store to store time stamps of detected events and to provide the interface with the time stamp of the detected event of the request.

9. The apparatus of claim 7 further comprising an event store to store time stamps of detected events and to provide the interface with the time stamp of the detected event of the request in response receiving an event identifier for the detected event from the interface.

10. The apparatus of claim 9 wherein the interface receives the event identifier for the detected event in the request for the detected event.

11. The apparatus of claim 7 further comprising an event store to store time stamps and associated event identifiers of detected events and to provide the interface with the time stamp of the detected event of the request in response receiving an event identifier for the detected event from the interface.

12. The apparatus of claim 7 wherein the controller provides a detected event with a time stamp in response to determining that the detected event is of an event type to be time stamped.

13. The apparatus of claim 12 wherein the controller ignores a detected event without providing the detected event with a time stamp in response to determining that the detected event is not of an event type to be time stamped.

14. The apparatus of claim 13 wherein the event types to be time stamped by the controller are programmable.

15. The apparatus of claim 7 incorporated into a chipset to couple a processor to other components of a computing device.

16. The apparatus of claim 7 incorporated into an arbiter to arbitrate access to a shared resource based upon arbitration events.

17. The apparatus of claim 7 incorporated into an interrupt controller to control interrupt events.

18. A system comprising

a network interface to receive at a program clock rate a stream comprising data blocks and program clock rate stamps indicative of the program clock rate,

a reference clock to generate a reference clock signal,

a device to process the data blocks of the stream at a processing rate set by the reference clock signal and to cause events indicative of the processing rate, and

a time-stamping circuit to detect the events indicative of the processing rate and to store time stamps for the events that are based upon the reference clock signal.

26. The system of claim 18 wherein the time-stamping circuit stores a time stamp for a detected event in response to determining that the detected event is of an event type to be time stamped.

27. The system of claim 26 wherein the time-stamping circuit ignores a detected event without storing a time stamp for the detected event in response to determining that the detected event is not of an event type to be time stamped.

29. The system of claim 18 further comprising an arbiter that comprises the time-stamping circuit and that arbitrates requests for a shared resource, wherein the time-stamping circuit stores time stamps for detected arbitration signals of an event type.

30. The system of claim 18 further comprising an interrupt controller that comprises the time-stamping circuit and that process interrupts received from the device, wherein the time-stamping circuit stores time stamps for detected interrupt signals of an event type.

19. The system of claim 19 wherein time-stamping circuit detects the events indicative of the processing rate based upon event types programmed into the time-stamping circuit.

20. The system of claim 19 further comprising a processor to request the time-stamping circuit for the time stamps for the events indicative of the processing rate.

21. The system of claim 20 wherein the processor adjusts the processing rate based upon the time stamps for the events and the program clock rate stamps of the stream.

22. The system of claim 20 wherein the processor adjusts a frequency of the reference clock signal based upon the time stamps for the events and the program clock rate stamps of the stream.

23. The system of claim 20 wherein the processor resamples the data blocks based upon the time stamps for the events and the program clock rate stamps of the stream.

24. The system of claim 20 wherein the time-stamping circuit stores time stamps of detected events and provides the processor with a stored time stamp for a detected event in response to the processor requesting a time stamp from the time-stamping circuit.

25. The system of claim 20 wherein the time-stamping circuit stores time stamps of detected events and provides the processor with a stored time stamp of a detected event in response to the processor providing the time-stamping circuit with an event identifier for the detected event.

28. The system of claim 20 further comprising a chipset that comprises the time-stamping circuit and that couples the processor to the network interface and the device.

31. A machine-readable media comprising a plurality of instructions that, in response to being executed by a computing device, result in the computing device

requesting a time-stamping circuit for a time stamp of a detected event that is indicative of a processing rate for a stream,

determining the processing rate for the stream based upon the time stamp of the detected event,

determining a program clock rate for the stream based upon a program clock rate stamp of the stream, and

adjusting the processing rate for the stream in response to the processing rate and the program clock rate having a determined difference.

32. The machine-readable media of claim 31 wherein the plurality of instructions further result in the computing device adjusting the processing rate by resampling data blocks of the stream.

33. The machine-readable media of claim 31 wherein the plurality of instructions further result in the computing device adjusting a reference clock that controls the processing rate.

34. The machine-readable media of claim 31 wherein the plurality of instructions further result in the computing device programming the time-stamping circuit to stamp interrupt events indicative of the processing rate for the stream.

35. The machine-readable media of claim 31 wherein the plurality of instructions further result in the computing device programming the time-stamping circuit to stamp arbitration events indicative of the processing rate for the stream.