System for optimizing anti-fuse repair time using fuse id
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Accused Products
Abstract
A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.
26 Citations
60 Claims
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1-32. -32. (canceled)
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33. A method for testing a plurality of integrated circuits, including the steps of:
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performing a plurality of tests on the plurality of integrated circuits, each of said integrated circuits having a unique identifier stored in a machine readable device;
identifying integrated circuits that failed at least one of the plurality of tests by reading said unique identifier and identifying tests failed by the integrated circuits; and
for each of said plurality of integrated circuits which has failed at least one of the plurality of tests, creating a set of at least one test as a function of the unique identifier of a failed chip and repeating said set of at least one test the failed chip. - View Dependent Claims (34, 35, 36, 37, 38, 39)
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40. An apparatus for testing a plurality of integrated circuits, comprising:
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means for performing a plurality of tests on the plurality of integrated circuits;
means for reading a unique identifier from each integrated circuits that failed at least one of the plurality of tests and identifying tests failed by the integrated circuits; and
means for repeating at least one identified failed test on each of the integrated circuits which failed at least one test. - View Dependent Claims (41, 42, 43, 44, 45, 46)
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47. An apparatus for testing a plurality of integrated circuits, said apparatus comprising:
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a testing device for performing a plurality of tests on said plurality of integrated circuits, each of said plurality of integrated circuits having a unique circuit identifier stored in an identification circuit; and
a processor to control said testing device, said processor identifying each of said plurality of integrated circuits that failed at least one of said plurality of tests and identifying tests failed by each of said plurality of integrated circuits, wherein said testing device repeats at least one identified failed test on each integrated circuits that failed at least one of said plurality of tests. - View Dependent Claims (48, 49, 50, 51, 52, 53)
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54. A system comprising:
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a device tester adapted to perform a principal functional test on an integrated circuit having one or more functional circuit portions and produce principal result information indicating respective operation or failure of said one or more functional circuit portions;
a reader adapted to read an identification device on said integrated circuit so as to ascertain an identity of said integrated circuit; and
a recording medium adapted to record said identity and said result information and maintain an association therebetween. - View Dependent Claims (55, 56, 57, 58, 59, 60)
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Specification