Field effect transistor and manufacturing method thereof

• US 20050093033A1
• Filed: 09/03/2004
• Published: 05/05/2005
• Est. Priority Date: 09/05/2003
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kinoshita, Atsuhiro, Koga, Junji
• Granted Patent: US 7,119,402 B2
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66643 with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78645 with multiple gate

Abstract

A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

Claims

1. A field effect transistor comprising:

a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region;

a source electrode and a drain electrode which are formed on both sides of the first semiconductor region in a position corresponding to the gate electrode, and

second semiconductor regions each formed between the first semiconductor region and a corresponding one of the source electrode and the drain electrode, and having an impurity concentration higher than the first semiconductor region,

wherein portions of the second semiconductor regions which are formed in contact with the first semiconductor region are fully depleted in a channel lengthwise direction in a no-voltage application state.

2. The field effect transistor according to claim 1, wherein the source electrode and the drain electrode are formed to sandwich the first semiconductor region in the channel lengthwise direction.

3. The field effect transistor according to claim 1, wherein thickness of each of the portions of the second semiconductor regions is not larger than thickness of each of portions of the second semiconductor regions which is fully depleted in the channel lengthwise direction in equilibrium with respect to the source electrode.

4. The field effect transistor according to claim 2, wherein the thickness of each of the second semiconductor regions in the channel lengthwise direction is set to not larger than 10 nm and set to a value smaller than a depletion layer width determined by the impurity concentration.

5. The field effect transistor according to claim 4, wherein the impurity concentration of the second semiconductor regions is set to a value not lower than 4×

10¹⁹ cm<sup>−

3</sup>.

6. The field effect transistor according to claim 5, wherein the depletion layer width W determined by the impurity concentration is defined by

W=2×

(ε

_s·

Eg/q·

N)^1/2

when the impurity concentration of the second semiconductor regions is set to N, a dielectric constant is set to ε

_s, a band gap is set to Eg, and an elementary charge is set to q.

7. A field effect transistor comprising:

a first semiconductor region forming a channel region,

a gate electrode formed above the first semiconductor region,

a source electrode and a drain electrode which are formed, respectively, on both sides of the first semiconductor region in position corresponding to the gate electrode, and

second semiconductor regions each formed between the first semiconductor region and a corresponding one of the source electrode and the drain electrode, and having a higher impurity concentration than the first semiconductor region,

wherein the following relation holds;

Wj≦

2×

(ε

_s·

Eg/q·

N)^1/2

where Wj is a thickness of the second semiconductor region in a carrier-propagating direction, N is an impurity concentration, ε

_s is a dielectric constant, Eg is a band gap, and q is an elementary charge, and

the thickness Wj is at most 10 nm, or the impurity concentration N is at least 4×

10¹⁹ cm<sup>−

3</sup>.

8. A field effect transistor comprising:

a first semiconductor region forming a channel region,

a gate electrode insulatively disposed above the first semiconductor region,

a source electrode and a drain electrode which are formed, respectively, on both sides of the first semiconductor region in position corresponding to the gate electrode, and

second semiconductor regions each formed between the first semiconductor region and a corresponding one of the source electrode and the drain electrode, and having a higher impurity concentration than the first semiconductor region,

wherein the second semiconductor region has impurity concentration N that is at least 4×

10¹⁹ cm<sup>−

3</sup>, and a distance Ws between a lower surface of the gate electrode and each of the source electrode and the drain electrode is given by;

Ws≦

2×

(ε

_s·

Eg/q·

N)^1/2

where ε

_s is a dielectric constant of the second semiconductor region and q is an elementary charge.

9. The field effect transistor according to claim 8, wherein the first semiconductor region, the second semiconductor region, the source electrode and the drain electrode are formed on an insulating film.

10. A field effect transistor manufacturing method comprising:

disposing a gate electrode insulatively above a part of a first semiconductor region made of Si,

ion-implanting impurity into the first semiconductor region with the gate electrode used as a mask,

carrying out heat treatment to activate the ion-implanted impurity, and

forming source and drain electrodes by siliciding a region corresponding to an ion-implanted portion of the first semiconductor region to a depth larger than a depth of the ion-implanted portion; and

forming second semiconductor regions in interfaces each between the first semiconductor region and a corresponding one of the source and drain electrodes to a thickness by which the second semiconductor regions are fully depleted in a no-voltage application state, by segregation of the impurities which is due to the siliciding.

11. A field effect transistor of a CMOS structure having an nMOS field effect transistor and pMOS field effect transistor, comprising:

an nMOS portion which includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, a first source electrode and a first drain electrode which are formed of first metal and sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions each formed between the first semiconductor region and a corresponding one of the first source electrode and the first drain electrode, and having an impurity concentration higher than that of the first semiconductor region, and

a pMOS portion which includes a third semiconductor region forming a channel region, a gate electrode insulatively disposed above the third semiconductor region, and a second source electrode and a second drain electrode which are formed of second metal and sandwich the third semiconductor region in a channel lengthwise direction,

wherein the first source electrode and the first drain electrode of the nMOS portion and the second source electrode and the second drain electrode of the pMOS portion are formed of the same material.

12. The field effect transistor according to claim 11, wherein the impurity concentration of the second semiconductor region is set to a value not lower than 4×

10¹⁹ cm<sup>−

3</sup> and the thickness of the second semiconductor region in the channel lengthwise direction is set to a value not larger than 10 nm.

13. The field effect transistor according to claim 11, wherein the following relation holds:

Wj≦

2×

(ε

_s·

Eg/q·

N)^1/2

where Wj is a thickness of the second semiconductor region in a carrier-propagating direction, N is an impurity concentration, ε

_s is a dielectric constant, Eg is a band gap, and q is an elementary charge, and

the thickness Wj is at most 10 nm, or the impurity concentration N is at least 4×

10¹⁹ cm<sup>−

3</sup>.

14. The field effect transistor according to claim 11, wherein the second semiconductor region has an impurity concentration N that is at least 4×

10¹⁹ cm<sup>−

3</sup>, and the distance Ws between a lower surface of the gate electrode and each of the source electrode and the drain electrode is given by;

Ws≦

2×

(ε

_s·

Eg/q·

N)^1/2

where ε

_s is a dielectric constant of the second semiconductor region and q is an elementary charge.

15. The field effect transistor according to claim 11, wherein the source electrode and the drain electrode have a higher impurity concentration than that of the third semiconductor region, and a peak impurity concentration at an interface with respect to the third semiconductor region or at a position near the interface.

16. The field effect transistor according to claim 15, wherein the semiconductor region is made of Si, Ge, C or a compound thereof.

17. The field effect transistor according to claim 16, wherein the source electrode and the drain electrode are made of silicide selected from the group consisting of Y silicide, Gd silicide, Tb silicide, Dy silicide, Ho silicide, Er silicide, Tm silicide, Yb silicide, Lu silicide, Co silicide, Ni silicide, Pb silicide, Pt silicide, Os silicide, Ir silicide and Re silicide.

18. The field effect transistor according to claim 17, wherein the impurity is at least one selected from the group consisting of B (boron), P (phosphorus), As (arsenic), O (oxygen), N (nitrogen), In (indium), Ga (gallium) and Pb (antimony).

19. The field effect transistor according to claim 17, wherein at least one of the first semiconductor region, the second semiconductor region, the third semiconductor region, the first source electrode, the second source electrode, the first drain electrode and the second drain electrode is provided on an insulating layer.

20. A field effect transistor comprising:

a semiconductor region forming a channel region having an impurity concentration,

a gate electrode insulatively disposed above the semiconductor region, and

a source electrode and a drain electrode which are made of metal and formed on both sides of a portion of the semiconductor region which corresponds in position to the gate electrode,

wherein the source electrode and the drain electrode each have an impurity concentration higher than the impurity concentration of the channel region, and a peak of the impurity concentration lies(?) at or near an interface with respect to the channel region and a corresponding one of the source electrode and the drain electrode.

21. The field effect transistor according to claim 20, wherein the source electrode and the drain electrode are formed to sandwich the semiconductor region in the channel lengthwise direction.

22. The field effect transistor according to claim 20, wherein impurity contained in each of the source electrode and the drain electrode modulates height of a Schottky barrier in the interface between the semiconductor region and each of the source electrode and the drain electrode.

23. The field effect transistor according to claim 20, wherein the semiconductor region is made of Si, Ge, C or a compound thereof, and the source electrode and the drain electrode are made of metal or compound of the metal and the semiconductor.

24. The field effect transistor according to claim 22, wherein the impurity which modulates the height of the Schottky barrier is at least one selected from the group consisting of B (boron), P (phosphorus), As (arsenic), O (oxygen), N (nitrogen), In (indium), Ga (gallium) and Sb (antimony).

25. The field effect transistor according to claim 24, wherein the channel region is formed of an n-type region, the source electrode and the drain electrode are made of at least one silicide selected from the group consisting of Er silicide, Y silicide, Gd silicide, Tb silicide, Dy silicide, Ho silicide, Tm silicide, Yb silicide and Lu silicide.

26. The field effect transistor according to claim 24, wherein the source electrode and the drain electrode are made of at least one silicide selected from the group consisting of Pt silicide, Ni silicide, Pd silicide, Os silicide, Ir silicide and Re silicide.