CMOS image sensor and method for fabricating the same

• US 20050093036A1
• Filed: 11/04/2004
• Published: 05/05/2005
• Est. Priority Date: 11/04/2003
• Status: Active Grant

• Current Assignee: Columba Technologies, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Han, Chang Hun
• Granted Patent: US 7,354,789 B2
• Time in Patent Office: Days
• US Class Current: 257/291
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

CMOS image sensor and method for fabricating the same, the CMOS image sensor including a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein, a device isolating film in the semiconductor substrate of the device isolation region, a first conductive type impurity region in the semiconductor substrate of the photodiode region, the first conductive type impurity region being spaced a distance from the device isolation film, and a second conductive type first impurity region in the semiconductor substrate between the first conductive type impurity region and the device isolation film, thereby reducing generation of a darkcurrent at an interface between the photodiode region and a field region.

Claims

1. A CMOS image sensor comprising:

a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein;

a device isolating film in the semiconductor substrate of the device isolation region;

a first conductive type impurity region in the semiconductor substrate of the photodiode region, the first conductive type impurity region being spaced a distance from the device isolation film; and

a second conductive type first impurity region in the semiconductor substrate between the first conductive type impurity region and the device isolation film.

2. The CMOS image sensor as claimed in claim 1, wherein the second conductive type first impurity region has a depth the same with a depth of the first conductive type impurity region.

3. The CMOS image sensor as claimed in claim 1, wherein the second conductive type first impurity region has a depth the same with a depth of the device isolation film.

4. The CMOS image sensor as claimed in claim 1, further comprising a second conductive type second impurity region at a surface of the first conductive type impurity region in the photodiode region.

5. The CMOS image sensor as claimed in claim 4, wherein the second conductive type first impurity region has a width the same with a depth of the second conductive type second impurity region.

6. The CMOS image sensor as claimed in claim 4, wherein the second conductive type first impurity region has an impurity concentration heavier than an impurity concentration of the second conductive type second impurity region.

7. The CMOS image sensor as claimed in claim 4, wherein the second conductive type first impurity region has an impurity concentration the same with an impurity concentration of the second conductive type second impurity region.

19. The CMOS image sensor as claimed in claim 1, wherein the second conductive type first impurity region has a depth deeper than a depth of the device isolation film.

8. A method for fabricating a CMOS image sensor, comprising the steps of:

forming a device isolation film in a device isolation region of a second conductive type semiconductor substrate, for defining an active region having a photodiode region and a transistor region;

forming a gate insulating film and a gate electrode on the semiconductor substrate of the transistor region;

forming a lightly doped first conductive type impurity region in the semiconductor substrate of the photodiode region;

forming a medium concentration second conductive type impurity region at a surface of the lightly doped first conductive type impurity region; and

forming a heavily doped second conductive type impurity region in the substrate of the photodiode region adjacent to the device isolation film.

9. The method as claimed in claim 8, wherein the heavily doped second conductive type impurity region has a width the same with a depth of the medium concentration second conductive type impurity region.

10. The method as claimed in claim 8, wherein the heavily doped second conductive type impurity region has a depth the same with a depth of the device isolation film, or a depth of the lightly doped first conductive type impurity region.

11. A method for fabricating a CMOS image sensor, comprising the steps of:

forming a device isolation film in a device isolation region of a second conductive type semiconductor substrate, for defining an active region having a photodiode region and a transistor region;

forming a gate insulating film and a gate electrode on the semiconductor substrate of the transistor region;

forming a lightly doped first conductive type impurity region in the semiconductor substrate of the photodiode region;

forming an insulating layer on an entire surface of the substrate inclusive of the gate electrode;

selectively removing the insulating layer to expose the device isolating film and a predetermined portion of the photodiode region adjacent to the device isolating film;

forming a phtoresist film pattern to expose the photodiode region on the insulating layer; and

injecting second conductive type impurity ions at a medium concentration into the photodiode region by using the insulating layer and the photoresist pattern as a mask, to form medium concentration second conductive type impurity regions at an interface of the device isolating film and the photodiode region, and at a surface of the lightly doped first conductive type impurity region.

12. The method as claimed in claim 11, wherein the medium concentration second conductive type impurity region at the interface of the device isolating film and the photodiode region has a depth deeper than a depth of the medium concentration second conductive type impurity region at the surface of the lightly doped first conductive type impurity region.

13. The method as claimed in claim 11, wherein the medium concentration second conductive type impurity region at the interface of the device isolating film and the photodiode region has a depth the same with a depth of the device isolation film.

14. The method as claimed in claim 11, wherein the medium concentration second conductive type impurity region at the interface of the device isolating film and the photodiode region has a width the same with a depth of the medium concentration second conductive type impurity region at the surface of the lightly doped first conductive type impurity region.

15. The method as claimed in claim 11, wherein the insulating film exposes the photodiode region by a width in a range of 400˜

600 Å

.

16. The method as claimed in claim 11, wherein the insulating film is one of SiH₄ film, a USG (Undoped Silicate Glass) film deposited by chemical vapor deposition of high density plasma, a BPSG (Boro Phosphorous Silicate Glass) film, or TEOS (Tetra Ethyl Ortho Silicate) film.

17. The method as claimed in claim 11, wherein the insulating film has a thickness smaller than a depth of the device isolation film by 300˜

500 Å

.

18. The method as claimed in claim 11, wherein the insulating film has a thickness of 2000˜

3000 Å

.