Memory re-implementation for field programmable gate arrays
First Claim
1. A method of re-implementing at least one memory module having an undesirable timing delay, the at least one memory module being on an FPGA device, the FPGA device comprising generic logic blocks and dedicated logic blocks, the at least one memory module being implemented by a first set of at least one of the logic blocks, the at least one logic block of said first set has at least one critical pin, the method comprising:
- (a) identifying the at least one memory module;
(b) selecting a second set of logic blocks for use in re-implementing said at least one memory module, at least a first logic block of the said second set having a pin that is logically equivalent to said at least one critical pin of the at least one logic block of said first set, the first logic block of the second set being non-identical to the at least one logic block of the first set; and
(c) selectively re-implementing the at least one memory module using the second set of logic blocks in the event that re-implementation using the second set of logic blocks reduces the undesirable timing delay of the at least one memory module.
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Accused Products
Abstract
Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.
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Citations
65 Claims
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1. A method of re-implementing at least one memory module having an undesirable timing delay, the at least one memory module being on an FPGA device, the FPGA device comprising generic logic blocks and dedicated logic blocks, the at least one memory module being implemented by a first set of at least one of the logic blocks, the at least one logic block of said first set has at least one critical pin, the method comprising:
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(a) identifying the at least one memory module;
(b) selecting a second set of logic blocks for use in re-implementing said at least one memory module, at least a first logic block of the said second set having a pin that is logically equivalent to said at least one critical pin of the at least one logic block of said first set, the first logic block of the second set being non-identical to the at least one logic block of the first set; and
(c) selectively re-implementing the at least one memory module using the second set of logic blocks in the event that re-implementation using the second set of logic blocks reduces the undesirable timing delay of the at least one memory module. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of implementing one or more memory modules on an FPGA device comprising logic blocks, the method comprising:
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(a) generating an initial implementation of the one or more memory modules;
(b) performing physical timing analysis on the implementation;
(c) selecting one or more logic blocks on the FPGA that implement a memory module, or a part of a memory module;
(d) re-implementing, for the benefit of circuit delay reduction, the memory module or a part of the memory module, the act of re-implementing comprising replacing at least one of the selected one or more logic blocks with at least one different replacement logic block to provide a modified set of one or more logic blocks and rearranging the modified set of logic blocks based on physical timing analysis; and
(e) re-connecting the modified set of logic blocks of the re-implemented memory module or part of the memory module on the FPGA device based on physical timing analysis. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22)
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23. A method of re-implementing a memory module, or part of a memory module, that has been implemented on an FPGA device at least in part by a first dedicated memory logic block, the FPGA device comprising plural logic blocks including the first dedicated memory logic block, the method comprising:
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(a) identifying the most critical pin of the first dedicated memory logic block;
(b) separating the said most critical pin from the said first dedicated memory logic block, the act of separating comprising substituting two or more logic blocks on the FPGA for said first dedicated memory block, the substituted two or more logic blocks realizing the same logic functions of the memory module or the said part of the memory module, wherein the substituted two or more logic blocks may realize the function of a portion of said first dedicated memory logic block; and
(c) placing the substituted two or more logic blocks to available locations on the FPGA device and re-connecting the substituted two or more logic blocks, based on timing analysis, to thereby re-implement the memory module and so as to reduce timing delay. - View Dependent Claims (24, 25, 26, 27)
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28. A method of re-implementing a memory module, or a part of a memory module, that has been implemented on an FPGA device by a first dedicated memory logic block, and whose most critical pin is a data input or output, the FPGA device comprising dedicated and generic logic blocks including the first dedicated memory logic block, the method comprising:
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(a) dividing the said memory module or the said part of a memory module into at least two parts, with a first part comprising the memory cells accessed via the said most critical pin, and the second part comprising the memory cells accessed via other data pins other than the said most critical pin;
(b) re-implementing the second part using the first dedicated memory logic block;
(c) re-implementing the first part using logic blocks other than the first dedicated memory logic block; and
(d) placing the logic blocks implementing the first part to advantageous locations on the FPGA device, and re-connecting the signals, based on physical timing analysis. - View Dependent Claims (29, 30, 31)
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32. A method of re-implementing a memory module, or a part of a memory module, that has been implemented on an FPGA device by a first dedicated memory logic block, and whose most critical pin is a read address, the FPGA device comprising dedicated and generic logic blocks including the first dedicated memory logic block, the method comprising:
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(a) dividing the said memory module or the said part of a memory module into the at least two parts, with a first part (Part
1) comprising the memory cells which are accessible when the address signal at the critical pin and address corresponds to a logic value 0, and a second part (Part
2) comprising the memory cells which are accessible when the address signal at the critical pin read address corresponds to a logic value 1;
(b) re-implementing the first part (Part
1) and the second (Part
2) using plural logic blocks to integrate the functioning of the first part (Part
1) and second part (Part
2) as the re-implemented memory module or re-implemented part of the memory module;
(c) providing a multiplexer, which is realized by a logic block or a portion of a logic block, for each data output related to the said address signal to select the corresponding data output from the first part (Part
1) when the said address signal corresponds to a logic value 0, or from the second part (Part
2) when the said address signal corresponds to a logic value 1; and
(d) placing the logic blocks comprising the memory module or part of the memory module to available locations on the FPGA, and re-connecting the signals based on timing analysis to minimize circuit delay. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40, 41, 45)
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42. A method of re-implementing a memory module, or a part of a memory module, that has been implemented on an FPGA by a dedicated memory block, and wherein the most critical pin is other than a data input pin or data output pin or read address pin, the FPGA device comprising distributed generic logic blocks and dedicated memory blocks, the method comprising:
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(a) re-implementing the said memory module or the said part of a memory module with the re-implementation of said memory module or the said part of said memory module comprising generic logic blocks and without using dedicated memory logic blocks; and
(b) placing the logic blocks that re-implement the memory module or the said part of a memory module on the FPGA device and reconnecting the signal, based on timing analysis;
so as to reduce circuit delay. - View Dependent Claims (43, 44)
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46. A method of re-implementing a memory module, or a part of a memory module, that has been implemented on an FPGA device, the FPGA device comprising dedicated and generic logic blocks, the memory module, or part of a memory module, having been implemented by a first set of one or more generic logic blocks, the method comprising:
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(a) identifying additional generic logic blocks, which together with the first set of generic logic blocks, implement the said memory module or the said part of a memory module;
(b) re-implementing the said memory module or the said part of a memory module using one or more logic blocks comprising at least one dedicated logic block; and
(c) placing the logic blocks used to re-implement the memory module or the said part of a memory module on the FPGA device, and re-connecting the signals, based on physical timing analysis, so as to reduce circuit delay. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
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65. An apparatus for re-implementing a memory module, or re-implementing a part of a memory module, that has been implemented on an FPGA device, the FPGA device comprising logic blocks, the apparatus comprising:
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(a) means for providing an initial implementation of the memory module or part of a memory module using a first set of logic blocks, the first set including at least one logic block; and
(b) means for re-implementing the memory module or part of a memory module using a second set of logic blocks which is not identical to the first set of logic blocks based on physical timing analysis and wherein the re-implementation reduces timing delay arising from the memory module or part of the memory module that is being re-implemented.
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Specification