Apparatus and method for reflection delay splitting digital clock distribution

• US 20050093592A1
• Filed: 10/30/2003
• Published: 05/05/2005
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Ungstad, Steve James
• Granted Patent: US 6,930,523 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A clock distribution system including a first and second phase detector. The first phase detector outputs a phase lead of an output clock signal. The second phase detector outputs a phase lag of a returned clock signal. Circuitry is included that propagates the output clock signal onto a transmission line based on the average the output of the first phase detector and the second phase detector.

Claims

1. A method of distributing a clock signal, the method comprising:

generating an output clock signal onto a transmission line;

detecting a returned clock signal;

detecting a first phase difference between a reference clock signal and the output clock signal;

detecting a second phase difference between the reference clock signal and the returned clock signal;

controlling the phase of the output clock signal based on an average of the first and second phase differences.

2. A method, as set forth in claim 1, further comprising obtaining the returned clock signal by sensing a reflection of the output clock signal on the transmission line.

3. A method, as set forth in claim 1, further comprising obtaining the returned clock signal from a return line matched to the transmission line.

4. A method, as set forth in claim 2, wherein the reflected signal is sensed by comparing the output clock signal with a composite signal from the transmission line, the composite signal including the output clock signal and a reflection of the output clock signal from the destination.

5. A method, as set forth in claim 1, wherein the step of controlling the phase of the output clock signal comprises driving a voltage controlled oscillator using the average of the first and second phase differences.

6. A method, as set forth in claim 5, further comprising buffering the output of the voltage controlled oscillator.

7. A method, as set forth in claim 5, further comprising buffering the output of the voltage controlled oscillator and providing a build out impedance to match the transmission line impedance.

8. A clock distribution circuit comprising:

a first phase detector that outputs a phase lead of an output clock signal;

a second phase detector that outputs a phase lag of a returned clock signal; and

circuitry that propagates the output clock signal onto a transmission line based on the average the output of the first phase detector and the second phase detector.

9. The clock distribution circuit, as set forth in claim 8, further comprising:

circuitry to detected the returned clock signal as a reflected clock signal on the transmission line.

10. The clock distribution circuit, as set forth in claim 8, further comprising:

a signal return line separate from the transmission line, wherein the returned clock signal is sensed from the signal return line.

11. The clock distribution circuit, as set forth in claim 10, wherein the signal return line is matched to the transmission line.

12. A clock distribution system comprising:

a reference clock that output a clock signal;

a first clock distribution circuit comprising;

a first phase detector that outputs a phase lead of a first output clock signal;

a second phase detector that outputs a phase lag of a first returned clock signal; and

first circuitry that propagates the first output clock signal onto a first transmission line based on the average the output of the first phase detector and the second phase detector;

a second clock distribution circuit comprising;

a third phase detector that outputs a phase lead of a second output clock signal;

a fourth phase detector that outputs a phase lag of a second returned clock signal; and

second circuitry that propagates the first output clock signal onto a second transmission line based on the average the output of the third phase detector and the fourth phase detector; and

wherein the first transmission line is a different length than the second transmission line and the first and second output clock signals coincide at the end of the first and second transmission line.

13. A method of distributing a reference clock signal, the method comprising:

sensing an output clock signal to be sent over a transmission line;

sensing a reflected clock signal at the beginning of the transmission line; and

adjusting the output clock signal based on an average of a first phase difference between the output clock signal and the reference clock signal and a second phase difference between the reflected clock signal and the reference clock signal.

14. A method of distributing a reference clock signal, the method comprising:

sensing an output clock signal to be sent over a transmission line;

sensing a returned clock signal at the end of a signal return line matched to the transmission line; and

adjusting the output clock signal based on an average of a first phase difference between the output clock signal and the reference clock signal and a second phase difference between the returned clock signal and the reference clock signal.