Driving IC of liquid crystal display

• US 20050093809A1
• Filed: 06/14/2004
• Published: 05/05/2005
• Est. Priority Date: 06/20/2003
• Status: Active Grant

• Current Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lim, Kyoung Moon
• Granted Patent: US 8,243,000 B2
• Time in Patent Office: Days
• US Class Current: 345/100
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A data driver IC of a liquid crystal display is provided. The data driver IC includes a latch circuit latching digital pixel data, a digital-to-analog converter converting an output of the latch circuit into an analog video signal, and an analog amplifier amplifying the analog video signal converted in the digital-to-analog converter. The analog amplifier includes a NAND gate, a capacitor connected to an input terminal of the NAND gate, and a switch for connecting the input terminal and an output terminal of the NAND gate.

Claims

1. A data driver IC for a liquid crystal display, comprising:

a latch circuit latching digital data;

a digital-to-analog converter converting an output of the latch circuit into an analog video signal; and

an analog amplifier amplifying the analog video signal converted in the digital-to-analog converter, wherein the analog amplifier comprises;

a NAND gate;

a capacitor connected to an input terminal of the NAND gate; and

a switch connecting the input terminal and an output terminal of the NAND gate.

2. The data driver IC according to claim 1, wherein the latch circuit comprises:

a data latch latching external digital data;

a shift register sequentially generating latch enable signals with respect to the digital data in synchronization with an external clock signal; and

a line latch sequentially storing the digital data that are input in synchronization with the latch enable signal.

3. The data driver IC according to claim 1, wherein the NAND gate has two input terminals that are connected to each other, such that the same analog video signal is input on both of the terminals.

4. The data driver IC according to claim 1, wherein the NAND gate comprises two input terminals, the analog video signal being input to a first input terminal, and an additional control signal being input to a second input terminal.

5. The data driver IC according to claim 4, wherein the first input terminal of the NAND gate is connected to an output terminal of the NAND gate by the switch.

6. The data driver IC according to claim 1, wherein a plurality of analog amplifiers are cascaded, each analog amplifier comprising:

a NAND gate;

a capacitor connected to an input terminal of the NAND gate; and

a switch connecting the input terminal and an output terminal of the NAND gate.

7. A data driver IC of a liquid crystal display, comprising:

a latch circuit latching digital data;

a digital-to-analog converter converting an output of the latch circuit into an analog video signal; and

an analog amplifier amplifying the analog video signal converted in the digital-to-analog converter,

wherein the analog amplifier comprises;

a NOR gate;

a capacitor connected to an input terminal of the NOR gate; and

a switch connected to the input terminal and an output terminal of the NOR gate.

8. The data driver IC according to claim 7, wherein the latch circuit comprises:

a data latch latching external digital data;

a shift register sequentially generating latch enable signals with respect to the digital data in synchronization with an external clock signal; and

a line latch sequentially storing the digital data that are input in synchronization with the latch enable signal.

9. The data driver IC according to claim 7, wherein the NOR gate has two input terminals that are connected to each other, such that the same analog video signal is input on both of the terminals.

10. The data driver IC according to claim 7, wherein the NOR gate comprises two input terminals, the analog video signal being input to a first input terminal, and an additional control signal being input to a second input terminal.

11. The data driver IC according to claim 10, wherein the first input terminal of the NOR gate is connected to an output terminal of the NOR gate by the switch.

12. The data driver IC according to claim 7, wherein a plurality of analog amplifiers are cascaded, each analog amplifier comprising:

a NOR gate;

a capacitor connected to an input terminal of the NOR gate; and

a switch connecting the input terminal and an output terminal of the NOR gate.