Method and apparatus for generating multi-phase signal

• US 20050094481A1
• Filed: 10/26/2004
• Published: 05/05/2005
• Est. Priority Date: 10/31/2003
• Status: Active Grant

• Current Assignee: Leader Electronics Corp.
• Original Assignee: Leader Electronics Corp.
• Inventors: Ishihara, Kenichi
• Granted Patent: US 7,193,449 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: H04B 17/3911 Fading models or fading generators

Abstract

A multi-phase signal generating apparatus is provided for readily generating multiple phase signals. The multi-phase signal generating apparatus comprises a signal data storage which stores a plurality of data segments for determining a predetermined period of one signal. A data segment selector circuit selects segments for constituting the phase signals from a plurality of data segments stored in the signal data storage for determining the predetermined period of a signal in each of a plurality of segment intervals which make up a phase signal cycle for generating a phase signal. Each phase signal generator circuit forms each phase signal using a plurality of selected segments for each phase signal during a plurality of segment intervals.

Claims

1. A method of generating a plurality of phase signals having different phases, said method comprising the steps of:

in each of a plurality of segment intervals constituting a phase signal cycle for generating said phase signals, selecting from a plurality of data segments defining a predetermined period of a single signal stored in a memory, a segment for constituting each of said phase signals and delivering the selected segment; and

generating each of said phase signals using a plurality of said selected segments for each of said phase signals during said plurality of segment intervals.

2. The method according to claim 1, wherein said selected segment constituting each of said phase signal in each of said segment intervals is selected depending on a phase difference between said plurality of phase signals.

3. The method according to claim 1, wherein each of said segment intervals includes a plurality of segment subintervals corresponding to said plurality of phase signals, respectively,

wherein said step of selecting a segment includes, for each of said phase signals, the step of reading said selected segment from said memory during said segment subinterval corresponding to each of said phase signal in each of said segment intervals.

4. The method according to claim 3, wherein said step of reading said selected segments includes:

defining a plurality of sequences of memory addresses for said plurality of phase signals; and

accessing said memory during said segment subintervals of said plurality of segment intervals using said sequence of memory addresses corresponding to each of said phase signals.

5. The method according to claim 4, wherein said plurality of sequences of memory addresses are shifted one after another by a predetermined amount corresponding to the phase difference between said plurality of phase signals.

6. The method according to claim 1, wherein said step of generating each of said phase signals includes the steps of:

acquiring and holding each of said selected segments for said plurality of phase signals from said memory; and

simultaneously outputting each of said selected segments for said plurality of phase signals at the end of each of said segment intervals.

7. The method according to claim 6, wherein said step of generating each of said phase signals further includes the step of interpolating said selected segments for each of said phase signals.

8. The method according to claim 7, wherein said interpolation uses an interpolation coefficient, and said interpolation coefficient is determined depending on the difference between adjacent ones of said data segments and the number of said plurality of phase signals.

9. The method according to claim 7, wherein;

each of said segment intervals is shorter than one cycle of each of said phase signals, and

said interpolation is performed at a shorter interpolation cycle than said segment interval.

10. The method according to claim 3, wherein each of said phase signals to be generated has a frequency, and wherein said selected segments are read from said memory at a reading rate which varies depending on the frequency.

11. The method according to claim 10, wherein the frequency of said phase signals varies in accordance with the Doppler frequency.

12. The method according to claim 1, wherein said plurality of phase signals comprise a multi-phase Gaussian noise signal.

13. The method according to claim 12, wherein said multi-phase Gaussian noise signal is used for applying a multipath fading effect.

14. The method according to claim 1, further including the step of:

storing said plurality of data segments in said memory, said data segments defining the predetermined period of said single signal.

15. An apparatus for generating a plurality of phase signals having different phases, said apparatus comprising:

a memory that stores a plurality of data segments for defining a predetermined period of a single signal;

a selector circuit that in each of a plurality of segment intervals constituting a phase signal cycle for generating said phase signals, selects from a plurality of data segments defining a predetermined period of a single signal stored in said memory a segment for constituting each of said phase signals and delivers the selected segment; and

a generator circuit that generates each of said phase signals using a plurality of said selected segments for each of said phase signals during said plurality of segment intervals.

16. The apparatus according to claim 15, wherein said selector circuit selects said selected segment constituting each of said phase signals in each of said segment intervals depending on a phase difference between said plurality of phase signals.

17. The apparatus according to claim 15, wherein each of said segment intervals includes a plurality of segment subintervals corresponding to said plurality of phase signals, respectively,

wherein said selector circuit includes a timing circuit that defines each of said segment intervals and said plurality of segment subintervals;

and

wherein said selector circuit includes, for each of said phase signals, a reading circuit that reads said selected segment from said memory during said segment subinterval corresponding to each of said phase signal in each of said segment intervals.

18. The apparatus according to claim 17, wherein said reading circuit includes:

an address generator circuit that defines a plurality of sequences of memory addresses for said plurality of phase signals; and

an accessing circuit that accesses said memory during said segment subintervals of said plurality of segment interval using said sequence of memory addresses corresponding to each of said phase signals.

19. The apparatus according to claim 18, wherein said address generator circuit includes a plurality of memory address sequence generator circuits corresponding to said plurality of phase signals, respectively, said plurality of sequences of memory addresses being shifted one after another by a predetermined amount corresponding to the phase difference between said plurality of phase signals.

20. The apparatus according to claim 15, wherein said selector circuit includes:

an acquisition circuit that acquires and holds each of said selected segments for said plurality of phase signals from said memory; and

an output circuit that simultaneously output each of said selected segments for said plurality of phase signals at the end of each of said segment intervals.

21. The apparatus according to claim 20, wherein said generator circuit further includes an interpolator circuit that interpolates said selected segments for each of said phase signals.

22. The apparatus according to claim 21, wherein;

said interpolator circuit includes interpolation coefficient generator circuit for generating an interpolation coefficient said interpolation coefficient being determined depending on the difference between adjacent ones of said data segments and the number of said plurality of phase signals.

23. The apparatus according to claim 17, wherein each of said phase signals to be generated has a frequency, said apparatus further includes a timing circuit that determines a variable reading rate for reading from said memory, said reading rate being variable depending on the frequency,

and wherein said reading circuit operates at a variable reading rate.

24. The apparatus according to claim 15, further including a writing circuit that writes said plurality of data segments for defining the predetermined period of said single signal into said memory.

25. An apparatus for generating a plurality of phase signals having different phases, said apparatus comprising:

means for storing a plurality of data segments for defining a predetermined period of a single signal;

means for, in each of a plurality of segment intervals constituting a phase signal cycle for generating said phase signals, selecting from a plurality of data segments defining a predetermined period of a single signal stored in said memory a segment for constituting each of said phase signals and delivering the selected segment; and

means for generating each of said phase signals using a plurality of said selected segments for each of said phase signals during said plurality of segment intervals.