Apparatus and method for automatic polarity swap in a communications system

• US 20050094734A1
• Filed: 10/29/2003
• Published: 05/05/2005
• Est. Priority Date: 10/29/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Parthasarathy, Vasudevan
• Granted Patent: US 7,430,240 B2
• Time in Patent Office: Days
• US Class Current: 375/257
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

An automatic polarity swap is implemented in a communications system. Two or more transceivers having differential inputs and outputs are coupled together through an interface, such as a backplane to form a communications system. In such a configuration, it is possible to cross-connect the differential data lines or signals at the interface, which will cause invalid data words to received at the second transceiver. Accordingly, the present invention includes an error check and correction module that detects invalid data words after parallel-to-serial conversion. More specifically, an error check determines if the parallel differential signal represents a valid data word. This can be done, for example, by storing and comparing valid data words in a memory such as RAM. If the received data word is valid, then no corrective action is taken. However, if the received data word is invalid, then the parallel differential signal is inverted using a logic circuit, which will correct the error if it is due to cross-connection of the differential lines at the interface or anywhere else.

Claims

1. A method of processing a data signal, comprising:

receiving a differential data signal;

determining if said differential data signal represents a valid data word; and

if said differential data signal does not represent a valid data word, then inverting said differential data signal, producing an inverted differential data signal.

2. The method of claim 1, wherein said step of inverting includes the step of X-ORing said data differential data signal with a control bit, said control bit being a logic “

1”

if said differential data signal represents an invalid data word.

3. The method of claim 2, wherein said control bit is a logic “

0”

if said differential data signal represents a valid data word.

4. The method of claim 1, further comprising the step of further processing said inverted differential data signal.

5. The method of claim 1, further comprising the step of serializing said inverted differential data signal.

6. The method of claim 5, further comprising the step of transmitting the result of said serializing step to a destination node.

7. The method of claim 1, wherein said step of determining comprises the step of comparing a data word represented by said differential data signal with one or more valid data words stored in a memory.

8. The method of claim 7, further comprising the step of generating a control signal based on said step of comparing.

9. The method of claim 7, wherein said control signal represents a logic “

1”

if said data word represented by said differential data signal is not consistent with at least one of said valid data words, and wherein said control signal represents a logic “

0”

if said data word is consistent with at least one of said one or more valid data words.

10. The method of claim 1, further comprising the step of determining if said inverted differential data signal represents a valid data word.

11. The method of claim 10, further comprising the step of further processing said inverted differential data signal if said inverted differential data signal represents a valid data word.

12. The method of claim 1, wherein said differential data signal includes a first component and a second component, and wherein said step of inverting comprises the step of inverting a logic state of said first component of said differential data signal, and inverting a logic state of said second component of said differential data signal.

13. A method of processing a data signal, comprising:

receiving a differential data signal having a first component and a second component;

comparing a data word represented by said differential data signal with one or more valid data words;

if said data word of said differential data signal is not consistent with at least one of said one or more valid data words, then inverting said first component and said second component of said differential data signal, producing an inverted differential data signal.

14. The method of claim 13, further comprising the steps of:

generating a control signal if said data word of said differential data signal is not consistent with at least one of said one or more valid data words, said control signal having a logic state “

1”

; and

X-ORing said control signal with said first and second components of said differential data signal to produce said inverted differential data signal.

15. A transceiver, comprising:

a receiver input for receiving a serial data signal;

a serial-to-parallel converter coupled to an output of said receiver input;

an error check for determining if a differential output of said serial-to-parallel converter represents a valid data word; and

a logic circuit for inverting said differential output if said differential output does not represent a valid data word.

16. The transceiver of claim 15, wherein said logic circuit includes a X-OR circuit having said differential output as a first input and a control signal as a second input.

17. The transceiver of claim 16, wherein said control signal causes said X-OR circuit to invert said differential output of said serial-to-parallel converter if said differential output does not represent a valid data word.

18. The transceiver of claim 17, wherein said control signal is a logic “

1”

if said differential output does not represent a valid data word, and said control signal is a logic “

0”

if said differential output represents a valid data word.

19. The transceiver of claim 17, wherein said error check includes a memory that stores one or more valid data words, and wherein said error check generates said control signal based on a comparison between said differential output and said one or more valid code words.

20. The transceiver of claim 19, wherein said error check generates said control signal to have a logic “

1”

if said differential output is not consistent with at least one of said valid code words.

21. A communications system, comprising:

a first transceiver;

a second transceiver; and

an interface coupled between said first transceiver and said second transceiver, said interface coupling a differential output of said first transceiver to a differential input of said second transceiver;

said second transceiver including a means for correcting said differential input of said second transceiver to compensating for a cross-connection of said differential output of said first transceiver to said differential input of said second transceiver at said interface.

22. The communications system of claim 21, wherein said means for correcting includes a means for inverting said differential input of said second transceiver when said differential output of said first transceiver and said differential input of said second transceiver are cross-connected.

23. The communications system of claim 22, wherein said means for inverting includes an X-OR logic circuit that inverts said differential input of said second transceiver responsive to a control signal.