Capacitor integration at top-metal level with a protection layer for the copper surface

• US 20050095781A1
• Filed: 10/30/2003
• Published: 05/05/2005
• Est. Priority Date: 10/30/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Burke, Edmund, Papa Rao, Satyavolu S., Rost, Timothy A.
• Granted Patent: US 7,015,093 B2
• Time in Patent Office: Days
• US Class Current: 438/250
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.

Claims

1. A method of fabricating an integrated circuit, comprising the steps of:

providing a semiconductor body having a top metal interconnect level formed thereon, said top metal interconnect level having a first and a second metal interconnect line;

depositing a material over said top metal interconnect level;

patterning and etching said material to expose a portion of said top metal interconnect level; and

forming a capacitor on said exposed portion of said top metal interconnect level, wherein said first metal interconnect line is protected by said material during said step of forming said capacitor.

2. The method of claim 1, wherein the step of forming said capacitor comprises the steps of:

depositing a bottom electrode material on said exposed portion of said top metal interconnect level;

forming a capacitor dielectric over said bottom electrode material;

depositing a top electrode material over said capacitor dielectric; and

patterning and etching said top electrode material, said capacitor dielectric, and said bottom electrode material to form said capacitor.

3. The method of claim 2, further comprising the steps of:

forming a protective overcoat over said top electrode and said top metal interconnect level;

forming a cap partially over said protective overcoat, said cap electrically connecting said top electrode material and said second metal interconnect line.

4. The method of claim 1, wherein said bottom electrode material and said top electrode material each comprise TaN.

5. The method of claim 1, wherein said bottom electrode material and said top electrode material each comprise one or more layers of material selected from the group consisting of TaN, TiN, Ir, Ru, and Ta.

6. The method of claim 1, wherein said capacitor dielectric layer comprises tantalum-oxide.

7. The method of claim 1, wherein said capacitor dielectric layer comprises hafnium-oxide or silicon nitride.

8. The method of claim 1, wherein said first and second metal interconnect lines comprise copper.

9. An integrated circuit comprising:

a topmost metal interconnect level located over a semiconductor body, said topmost metal interconnect level comprising a first and a second metal interconnect line;

a decoupling capacitor located over said topmost metal interconnect level, wherein a bottom electrode of said decoupling capacitor is electrically connected to said first metal interconnect line;

a protect layer on said second metal interconnect line;

an etchstop layer over said protect layer;

a protective overcoat over said etchstop layer; and

an aluminum cap layer located partially over said protective overcoat and electrically connecting a top electrode of said decoupling capacitor to said second copper interconnect line.

10. The integrated circuit of claim 9, wherein said top electrode and said bottom electrode comprise TaN.

11. The integrated circuit of claim 9, wherein said top electrode and said bottom electrode each comprise one or more layers of material selected from the group consisting of TaN, TiN, Ir, Ru, and Ta.

12. The integrated circuit of claim 9, wherein said capacitor dielectric comprises tantalum-oxide.

13. The method of claim 12, wherein said step of forming a capacitor dielectric comprises the steps of:

depositing a layer of tantalum-oxide over said bottom electrode; and

annealing said layer of tantalum-oxide in oxygen to reduce impurities and increase the oxygen content.

14. The integrated circuit of claim 9, wherein said capacitor dielectric comprises hafnium-oxide or silicon nitride.

15. The integrated circuit of claim 9, wherein said first and second metal interconnect lines comprise copper.