System and method for data synchronization for a computer architecture for broadband networks

• US 20050097302A1
• Filed: 10/18/2004
• Published: 05/05/2005
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Yamazaki, Takeshi, Suzuoki, Masakazu
• Granted Patent: US 7,457,939 B2
• Time in Patent Office: Days
• US Class Current: 712/34
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system is provided for processing programs and data. The processing system has a processing unit and multiple sub-processing units. Each sub-processing unit includes a dedicated local memory for storing programs and data. The dedicated local memory of each respective sub-processing unit is not a cache memory. In an alternative, multiple computing devices may connect to one another via a communications network, and each computing device may include at least one processing element having the processing unit and sub-processing units.

Claims

1. A processing system, comprising:

a processing unit; and

a plurality of sub-processing units for processing programs and data, each of the sub-processing units including a dedicated local memory for storing selected programs and data, and at least one of the sub-processing units being operable to communicate with the processing unit;

wherein the dedicated local memory of each respective sub-processing unit is not a cache memory.

2. A processing system, comprising:

a plurality of computing devices capable of connecting to one another via a communications network, each of the computing devices comprising at least one processing element, the at least one processing element comprising;

a processing unit; and

a plurality of sub-processing units for processing programs and data, each of the sub-processing units including a dedicated local memory for storing selected programs and data, and at least one of the sub-processing units being operable to communicate with the processing unit;

wherein the dedicated local memory of each respective sub-processing unit is not a cache memory.