Novel bisr mode to test the redundant elements and regular functional memory to avoid test escapes

• US 20050097417A1
• Filed: 11/04/2003
• Published: 05/05/2005
• Est. Priority Date: 11/04/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Puri, Mukesh K., Agrawal, Ghasi R.
• Granted Patent: US 7,913,125 B2
• Time in Patent Office: Days
• US Class Current: 714/733
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/838 with substitution of defective spares

Abstract

A BISR mode and associated method for testing memory. All redundant elements of the memory including the ones which are not used are tested, and interaction between redundant elements of the memory and adjacent functional memory are checked. Repair information is used to repair the memory. In addition, redundant elements which are not needed to be used for repairing the memory are forced to be used, such as by faking defects to remap good elements with redundant elements.

Claims

1. A BISR mode for testing memory, said BISR mode comprising:

means for testing all redundant elements of the memory including the ones which are not used; and

means for checking interaction between redundant elements of the memory and adjacent functional memory.

2. A BISR mode as recited in claim 1, further comprising means for using repair information to repair the memory.

3. A BISR mode as recited in claim 1, further comprising means for forcing usage of redundant elements which are not needed to be used for repairing the memory.

4. A BISR mode as recited in claim 3, wherein the means for forcing usage of redundant elements which are not needed to be used for repairing the memory comprises means for faking defects to remap good elements with redundant elements.

5. A BISR mode as recited in claim 2, further comprising means for forcing usage of redundant elements which are not needed to be used for repairing the memory.

6. A BISR mode as recited in claim 5, wherein the means for forcing usage of redundant elements which are not needed to be used for repairing the memory comprises means for faking defects to remap good elements with redundant elements.

7. A BISR mode as recited in claim 1, further comprising means for forcing usage of all redundant elements of the memory.

8. A method for testing memory, said method comprising:

testing all redundant elements of the memory including the ones which are not used; and

checking interaction between all redundant elements of the memory and adjacent functional memory.

9. A method as recited in claim 8, further comprising using repair information to repair the memory.

10. A method as recited in claim 8, further comprising forcing usage of redundant elements which are not needed to be used for repairing the memory.

11. A method as recited in claim 10, wherein the step of forcing usage of redundant elements which are not needed to be used for repairing the memory comprises faking defects to remap good elements with redundant elements.

12. A method as recited in claim 9, further comprising forcing usage of redundant elements which are not needed to be used for repairing the memory.

13. A method as recited in claim 12, wherein the step of forcing usage of redundant elements which are not needed to be used for repairing the memory comprises faking defects to remap good elements with redundant elements.

14. A method as recited in claim 8, further comprising forcing usage of all redundant elements of the memory.