Method and apparatus for selectively compacting test reponses
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Abstract
A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs.
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Citations
41 Claims
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1-21. -21. (canceled)
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22. An apparatus used in testing of integrated circuits, comprising:
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a selector circuit configured to receive test responses from a circuit under test; and
a spatial compactor coupled to the selector circuit, wherein the spatial compactor includes a feedback-free network of linear gates. - View Dependent Claims (23, 24, 25, 26, 27, 28)
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29. An apparatus used in testing of an integrated circuit, comprising:
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at least one spatial compactor configured to compress test responses; and
a selector circuit coupled to the spatial compactor, wherein the selector circuit is configured to receive one or more test responses from a circuit under test and to control the masking of one or more of the test responses. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37)
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38. A method for selectively compacting test responses of a circuit under test, comprising:
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receiving N test responses, the test responses resulting from application of predetermined test patterns to the circuit under test;
selectively preventing between 0 and N of the test responses from being passed to a spatial compactor while allowing the remaining test responses to be passed to the spatial compactor; and
spatially compacting the test responses passed to the spatial compactor. - View Dependent Claims (39, 40, 41)
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Specification