Semiconductor designing apparatus

• US 20050097495A1
• Filed: 10/08/2004
• Published: 05/05/2005
• Est. Priority Date: 10/10/2003
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Ishiyama, Yasuhiro
• Granted Patent: US 7,272,812 B2
• Time in Patent Office: Days
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A semiconductor designing apparatus capable of effectively performing a layout designing operation and capable of developing both a circuit designing operation and a layout designing operation at the same time is provided. When a layout designing operation as to a semiconductor memory circuit and a semiconductor analog circuit is manually carried out in a semi-automatic designing manner, since a layout is produced every function, both an internal arranging operation and an internal wiring operation of structural elements can be omitted; also, since the structural elements can be separated, an internal shape of the structural elements can be easily changed; also, since an attribute of an element is changed, a degree of freedom as to a designing operation can be improved; also, since an instance can be added to an element, an insertion such as a substrate contact which does not depend upon a circuit diagram can be added to an arbitrary portion; and further, since a layout designing operation is commenced before a circuit diagram is determined and thereafter matching of net connections is confirmed, both the circuit designing operation and the layout designing operation can be carried out at the same time, so that a designing time period can be shortened.

Claims

1. A semiconductor designing apparatus comprising:

a data processor, processing a data based upon an information entered from an input unit;

a circuit diagram database, storing a circuit diagram data;

a layout database, storing a layout data;

a circuit editor, executing a circuit editing operation with respect to the data processed by the data processor by employing the circuit database;

a layout editor, executing a layout editing operation with respect to the data processed by the data processor by employing the layout data; and

a sub-circuit recognizer, recognizing a sub-circuit every function from the circuit data contained in the data entered by the data processor.

2. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a element structure separating unit, separating an element structure of the sub-circuit every element.

3. The semiconductor designing apparatus as claimed in claim 2, further comprising:

a element attribute designator, changing an attribute of the element.

4. The semiconductor designing apparatus as claimed in claim 2, further comprising:

a instance adding unit, adding an instance to the element.

5. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a provisional net name generator, generating a provisional net list name in such a case that since an instruction for forming a layout having no circuit diagram is issued from the input unit and a new layout is formed by the layout editing means and a circuit is formed by the circuit editing means; and

a circuit net name judging unit, judging a relative relationship between a net list name of the circuit and a net list name of the layout.

6. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a net name adjustor, making a net list name of a circuit coincident with a net list name of a layout in such a case that an instruction for making the net list names of the circuit and the layout coincident with each other is issued from the input unit.

7. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a different point judging unit, operated in such that in the case that an instruction for displaying a different point between a circuit and a layout is issued from the input unit, the different point judging unit confirms a connection condition between the circuit and the layout based upon the circuit diagram information of the circuit editor and the layout information of the layout editor, and judges a different point in the connection condition of the circuit and the layout, and then highlights the judged different point.

8. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a prohibited input judging unit, operated in such a manner that while a circuit forming operation is carried out by the circuit editor in response to an instruction for forming a circuit diagram issued from the input unit, the prohibited input judging unit judges a prohibited input, and prohibits an editing operation in the circuit editor as to an item of the prohibited input.

9. The semiconductor designing apparatus as claimed claim 1, further comprising:

an icon link unit, displaying an icon image indicative of functions of various sorts of elements on an editing screen when either a circuit editing operation or a layout editing operation is carried out, and producing a layout corresponding to an element designated by a user within the icon image, and displaying the produced layout.

10. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a library designator, operated in such that in the case that a forming instruction is issued from the data processor, the library designator processes circuit data of the circuit diagram database and layout data of the layout database in the form of libraries respectively, the library-processed circuit data can be used in the circuit editor, and the library-processed layout data can be used in the layout editor.

11. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a design grid corrector, operated in such that in the case that an instruction for forming a layout is issued from the input unit and a layout forming operation is carried out by the layout editor without setting a grid, and thereafter, an instruction for designating a grid is issued from the input unit, the design grid corrector performs a grid designation for the layout data of the layout database.

12. The semiconductor designing apparatus according to claim 1, further comprising:

a function undefined portion forming unit, forming an undefined portion which has not yet been defined within a circuit as such a polygon data which has no relationship with a net list within a layout.

13. The semiconductor designing apparatus as claimed in claim 12, further comprising:

a cell-process executor, cell-processing the polygon data.

14. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a mutual display, operated in such that in the case that while an instruction for forming a layout is issued from the input unit, the layout is formed in the layout editor, and thereafter, another instruction for selectively displaying a circuit and a layout is issued from the input unit, the mutual display selectively mixes the display of the circuit with the display of the layout.

15. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a lock designator, operated in such that in the case that an instruction for locking in either a circuit or a layout is issued from the input unit, the lock designator locks a subject place of the circuit diagram database and a subject place of the layout database with respect to the corresponding circuit and the corresponding layout.

16. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a comment input unit, operated in such that in the case that an instruction for inputting a comment in either a circuit or a layout is issued from the input means, the comment input means inputs a comment in a subject place of the circuit diagram database and a subject place of the layout database with respect to the corresponding circuit and the corresponding layout.

17. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a layout database, storing a layout data of a wiring line layer; and

a use cell selector, operated in such that in the case that while an instruction for forming a layout is issued from the input unit, a layout forming operation is carried out in the layout editor, and thereafter, another instruction for designating a wiring layer to be used is issued from the input unit, the use cell selector selects layout data of the corresponding wiring layer from the layout database to apply the selected layout data to the layout editor.

18. The semiconductor designing apparatus as claimed in claim 1, further comprising:

a design process changing unit, operated in such that in the case that while an instruction for forming a layout is issued from the input unit, a layout forming operation is carried out under process condition which has been defined in the beginning by the layout editor, and thereafter, another instruction for changing the process condition is issued from the input unit, the design process changing unit changes the process condition with respect to the layout data of the layout database.