System and method for lithography simulation
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Abstract
There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
80 Citations
73 Claims
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1-35. -35. (canceled)
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36. A method for evaluating a design pattern on a photolithographic mask, the method comprising:
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generating a pixel-based bitmap of the design pattern on the photolithographic mask using an image of the photolithographic mask;
generating a simulated image of the design pattern in wafer resist using (1) the pixel-based bitmap of the design pattern on the photolithographic mask and (2) a relationship representing the imaging path of the projection and illumination optics of a photolithographic tool; and
comparing the simulated image of the design pattern in wafer resist and a design target on the wafer which corresponds to the design pattern on the photolithographic mask. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A system for evaluating a design pattern on a lithographic mask, the system comprising:
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a microprocessor subsystem, including a plurality of microprocessors; and
a plurality of accelerator subsystems, each accelerator subsystem includes a plurality of programmable integrated circuits configured to process a pixel-based bitmap of the design pattern on the lithographic mask in parallel, and each accelerator subsystem is connected to an associated microprocessor to calculate a portion of a simulated image of the design pattern in wafer resist using (1) a corresponding portion of the pixel-based bitmap representation of the design pattern which is generated using an image of the lithographic mask and (2) a relationship representing the imaging path of the projection and illumination optics of a photolithographic tool; and
a data processing system to compare the simulated image of the design pattern in wafer resist and a design target on the wafer which corresponds to the design pattern on the lithographic mask. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
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63. A method for evaluating a design pattern on a lithographic mask, the method comprising:
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generating a simulated image of the design pattern in wafer resist using (1) a pixel-based bitmap of the design pattern on the lithographic mask which is generated using an image of the lithographic mask and (2) a relationship representing the imaging path of the projection and illumination optics of a photolithographic tool; and
comparing the simulated image of the design pattern in wafer resist and a design target on the wafer which corresponds to the design pattern on the lithographic mask. - View Dependent Claims (64, 65, 66, 67, 68, 69, 70, 71, 72, 73)
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Specification