Ordering of high use program code segments using simulated annealing
First Claim
1. A method of ordering program code in a computer memory, the method comprising:
- selecting an ordering from among a plurality of orderings for a plurality of program code segments using a heuristic algorithm; and
ordering the plurality of program code segments in a memory of a computer using the selected ordering.
2 Assignments
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Accused Products
Abstract
An apparatus, program product and method utilize a heuristic-based algorithm such as simulated annealing to order program code segments in a computer memory to provide improved computer performance in terms of memory access, e.g., by minimizing cache misses or other memory-related performance penalties that may be present in a multi-level memory architecture. Program code is ordered in a computer memory by selecting an ordering from among a plurality of orderings for a plurality of program code segments using a heuristic algorithm, and ordering the plurality of program code segments in a memory of a computer using the selected ordering.
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Citations
31 Claims
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1. A method of ordering program code in a computer memory, the method comprising:
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selecting an ordering from among a plurality of orderings for a plurality of program code segments using a heuristic algorithm; and
ordering the plurality of program code segments in a memory of a computer using the selected ordering. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An apparatus, comprising:
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a processor; and
program code configured to be executed by the processor to optimize execution of program code in a computer of the type including a multi-level memory architecture by using a heuristic algorithm to select an ordering from among a plurality of orderings for a plurality of program code segments in the program code. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A program product, comprising:
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first program code configured to optimize execution of second program code in a computer of the type including a multi-level memory architecture by using a heuristic algorithm to select an ordering from among a plurality of orderings for a plurality of program code segments in the second program code; and
a signal bearing medium bearing the first program code. - View Dependent Claims (31)
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Specification