Three-dimensional memory

• US 20050099856A1
• Filed: 09/18/2003
• Published: 05/12/2005
• Est. Priority Date: 06/27/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M.
• Granted Patent: US 7,115,967 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D semiconductor memory is described having rail-stacks which define conductive lines and cells. The memory levels are organized in pairs with each pair showing common lines in adjacent levels.

Claims

1-40. -40. (canceled)

41. A three dimensional memory array comprising:

a plurality of memory level pairs;

each memory level pair including a plurality of memory cells disposed on a first and second level;

the memory cells on the first level being coupled to first lines and common lines; and

the memory cells on the second level being coupled to second lines and the common lines.

42. The array defined by claim 41, wherein each memory cell comprises a diode and a breached antifuse layer when programmed.

43. The array defined by claim 42, wherein the first lines are disposed above the common lines and the second lines are disposed below the common lines.

44. A memory disposed above a substrate comprising:

a plurality of memory levels organized as first alternate levels disposed between second alternate levels;

a plurality of two terminal memory cells incorporated into each of the levels;

one terminal of the cells in each of the first alternate levels and each of the second alternate levels being coupled to first lines shared by the cells in each pair of first and second alternate levels;

the other terminal of the cells in each of the first alternate levels being coupled to second lines; and

the other terminal of the cells in each of the second alternate levels being coupled to third lines.

45. The memory defined by claim 44, wherein each cell comprises, when programmed, a diode and an antifuse layer.

46. The memory defined by claim 45, wherein the diodes comprise an N−

region and a P+ region.

47. The memory defined by claim 46, wherein the N−

regions in the diodes in at least one of the first and second alternate levels has a smaller cross-section than the P+ region.

48. The memory defined by claim 45, wherein the antifuse layer comprises silicon dioxide.

49. The memory defined by claim 47, wherein the antifuse layer comprises silicon dioxide.

50. The memory defined by claim 46, wherein the diodes include polysilicon layers.

51. The memory defined by claim 50, wherein the polysilicon layers include an N−

layer and a P+ layer.

52. The memory defined by claim 51, wherein the first, second, and third lines comprise a silicide.

53. The memory defined by claim 52, wherein the silicide comprises titanium silicide.

54. The memory defined by claim 53, wherein the shared first lines contact the P+ layers.

56. The memory defined by claim 54, wherein each cell comprises, when programmed, a diode and a breached antifuse layer.

57. The memory defined by claim 56, wherein at least some of the diodes comprise two regions, one having a smaller cross-section than the other.

55. A memory disposed above a substrate comprising:

a plurality of memory levels organized as first alternate levels disposed between second alternate levels;

a plurality of two terminal memory cells incorporated into each of the levels;

one terminal of the cells in each of the first alternate levels and each of the second alternate levels being coupled to first lines shared by the cells in each pair of first and second alternate levels;

the other terminal of the cells in each of the first alternate levels being coupled to second lines;

the other terminal of the cells in each of the second alternate levels being coupled to third lines; and

an oxide layer disposed between each of the pair of first and second alternate levels.

58. A memory disposed above a substrate comprising:

a plurality of memory levels, each level having a plurality of two terminal memory cells;

each of the memory cells comprising a diode and a breached antifuse layer, when programmed;

one terminal of the cells in first alternate levels and second alternate levels of the memory levels being coupled to first lines, shared by the cells;

the other terminal of the cells in the first alternate levels being coupled to second lines in each of the first alternate levels; and

the other terminal of the cells in the second alternate levels being coupled to third lines in each of the second levels, such that cells in paired first and second alternate levels are coupled to shared first line and one of the second and third lines.

59. The memory defined by claim 58, wherein at least some of the diodes have two regions one of which has a smaller cross-section than the other.

60. In a three-dimensional memory array, two adjacent memory levels comprising:

a first plurality of parallel, spaced-apart rail-stacks;

a second plurality of parallel, spaced-apart rail-stacks perpendicular to the first rail stacks disposed above the first rail-stacks;

a third plurality of parallel, spaced-apart rail-stacks perpendicular to the second rail-stacks disposed above the second rail-stacks, the first, second, and third rail-stacks being of approximately the same height;

the first rail-stacks and a first portion of a second rail-stacks defining first cells in one of the two levels and the third rail-stacks and a second portion of the second rail-stacks defining second cells in the other level of the memory, and

the third rail-stacks including conductors shared by the first and second cells.

61. The array of claim 60, wherein each cell comprises a diode and a breached antifuse layer, when programmed.

62. The array of claim 61, wherein each diode includes a P+N−

junction.

63. The array of claim 62, wherein the antifuse layer of the cells comprises silicon dioxide.