Canceller circuit and controlling method

• US 20050099967A1
• Filed: 10/28/2004
• Published: 05/12/2005
• Est. Priority Date: 11/07/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Baba, Mitsuo
• Granted Patent: US 7,468,957 B2
• Time in Patent Office: Days
• US Class Current: 370/286
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers
• CPC Class Codes: H04B 3/32 Reducing cross-talk, e.g. by compensating

Abstract

Disclosed is a device in which overasampling is not needed and in which the echo/crosstalk of a continuous time analog waveform may be canceled at a baud rate. There are provided a continuous time analog subtractor, an AD converter for converting an analog signal from a subtractor to a digital signal, an adaptive filter receiving a digital output signal from the AD converter and an echo/crosstalk reference signal and having adaptively variable filter coefficients, a FIFO in which a digital output signal from the FIFO is written in first-in first-out and in which a write and read clocks are interchanged, a D/A converter for converting the digital output signal from the FIFO to an analog signal to output the analog signal, and first and second variable delay circuits for variably delaying an input clock signal to output the delayed signals as first and second clock signals. The first clock signal is supplied to the AD converter, adaptive filter and to the FIFO, while the second clock signal is supplied to the FIFO and to the DA converter as sampling clock. A received signal, containing the echo-crosstalk, and a replica signal of the echo-crosstalk, output from the D/A converter, is supplied to the subtractor. A true received signal, which is the received signal from which the echo/crosstalk has been cancelled, is supplied to the AD converter.

Claims

1. A canceller circuit comprising:

a subtractor, receiving an analog received signal and a replica signal of echo/crosstalk, for carrying out subtraction on the received signal and the replica signal in a continuous time analog domain;

an analog-to-digital converter for converting an analog signal output from said subtractor to a digital signal;

an adaptive filter, receiving an echo/crosstalk reference signal and an output signal of said analog-to-digital converter, for outputting the replica signal of echo/crosstalk, as a digital signal;

a digital-to-analog converter for receiving and converting a digital signal output from said adaptive filter, to an analog signal, and for supplying the analog signal to said subtractor as said replica signal of echo/crosstalk; and

a control circuit for variably controlling the sampling phase in said digital-to-analog converter independently of the sampling phase on the side of said analog-to-digital converter;

the phase of the signal waveform of the replica signal of said echo/crosstalk, output from said digital-to-analog converter, being controlled to be coincident with the phase of echo/crosstalk received.

2. The canceller circuit according to claim 1, further comprising

a circuit, receiving the digital signal output from said adaptive filter, for effecting clock signal replacement from a sampling clock signal on the side of said analog-to-digital converter to a sampling clock signal on the side of said digital-to-analog converter to send the received digital signal to said digital-to-analog converter based on the sampling clock signal on the side of said digital-to-analog converter.

4. The canceller circuit according to claim 1, wherein the sampling frequency on the side of said analog-to-digital converter and the sampling frequency on the side of said digital-to-analog converter is equal to the number of times of modulation per second, that is, a baud rate.

6. The canceller circuit according to claim 1, wherein said digital-to-analog converter includes a filter for outputting a continuous time analog signal obtained on cutting frequency components not lower than one-half the sampling frequency from a discrete time analog signal obtained on sampling an input discrete time digital signal.

7. The canceller circuit according to claim 1, wherein the received signal supplied to said subtractor has frequency components not lower than one half the sampling frequency cut off.

12. A transceiver apparatus including said canceller circuit as defined in claim 1.

13. A communication system including a hybrid circuit and a transceiver apparatus on each end of a communication channel formed by a cable or a wire;

said transceiver apparatus including said canceller circuit as defined in claim 1 to effect full-duplex bidirectional communication.

3. A canceller circuit comprising:

a subtractor for outputting an analog signal obtained on subtracting an analog signal supplied to a second terminal thereof from an analog signal supplied to a first terminal thereof;

an analog-to-digital converter having an analog input terminal for receiving the analog signal output from said subtractor, said analog-to-digital converter converting the received analog signal to a digital signal to output the digital signal at a digital output terminal thereof;

an adaptive filter having input terminals for receiving the digital output signal output from said analog-to-digital converter and an input echo/crosstalk reference signal and an output terminal for outputting a filter output as a digital signal;

a first-in first-out storage device, receiving the digital signal output from said adaptive filter, to effect writing of the received digital signal based on a write clock signal and to effect reading and outputting of the digital signal based on a read clock to effect clock replacement;

a digital-to-analog converter having a digital input terminal for receiving the digital signal output from said first-in first-out storage device, said digital-to-analog converter converting the received digital signal to an analog signal to output the analog signal at an analog output terminal thereof; and

first and second variable delay circuits for receiving an input clock signal in common and for variably delaying said input clock signal to output delayed input clock signals as first and second clock signals;

wherein said first clock signal, output from said first variable delay circuit, is supplied to said analog-to-digital converter and to said adaptive filter as respective sampling clocks, while said first clock signal is supplied to said first-in first-out storage device as said write clock signal;

wherein said second clock signal, output from said second variable delay circuit, is supplied to said first-in first-out storage device as said read clock signal, while being supplied as a sampling clock for said digital-to-analog converter;

wherein a received signal is supplied to said first input terminal of said subtractor;

wherein the analog signal output from said digital-to-analog converter is supplied to said second input terminal of said subtractor as a replica signal of echo/crosstalk; and

wherein a signal corresponding to a received signal from a counterpart device with echo/crosstalk cancelled out is supplied to said analog input terminal of said analog-to-digital converter.

5. The canceller circuit according to claim 3, wherein the frequency of said first and second clock signals is equal to the number of times of modulation per second, that is a baud rate.

8. The canceller circuit according to claim 3, wherein, in a training mode for phase control, control is performed so that:

(a) in such a state where said echo/crosstalk reference signal is not supplied to said adaptive filter, the received signal from the counterpart device is not supplied to said subtractor and said replica signal from said digital-to-analog converter is not supplied to said subtractor,

a signal formed solely by echo/crosstalk is supplied to a first input terminal of said subtractor, the delay of first variable delay circuit is variably controlled based on an output signal from said analog-to-digital converter, the phase of said first clock signal is variably controlled, the delay of said second variable delay circuit is not controlled, and an optimum sampling position of said echo/crosstalk in said analog-to-digital converter is detected;

(b) in such a state where a first input terminal of said subtractor is signal-less with there being no received signal nor the echo/crosstalk from said counterpart device, said echo/crosstalk reference signal being supplied to said adaptive filter and where the replica signal from said digital-to-analog converter is supplied to a second input terminal of said subtractor,

the delay of said second variable delay circuit is variably controlled based on said output signal of said analog-to-digital converter, the phase of said second clock signal is controlled, the delay of said first variable delay circuit is not controlled, and the phase of the replica signal, output from the digital-to-analog converter, is controlled to be coincident with the phase of the echo/crosstalk received; and

(c) the phase of said first and second clock signals is not controlled and is left unattended, with the echo/crosstalk and said replica signal being entered to the first and second input terminals of said subtractor, respectively;

said analog-to-digital converter is supplied with a difference signal of said echo/crosstalk and said replica signal, output from said subtractor; and

said adaptive filter is supplied with an output signal of said analog-to-digital converter as an error and with said echo/crosstalk reference signal and adaptively varying the filter coefficients for decreasing an error between a filter output signal and the echo/crosstalk as a target signal to effect equalization pull-in to cancel the echo/crosstalk from an output of said subtractor.

9. The canceller circuit according to claim 8, wherein

in a normal operating mode following the training mode for phase control, a received signal containing the echo/crosstalk is supplied to the first input terminal of said subtractor,

wherein said adaptive filter is supplied with said echo/crosstalk reference signal, said second input terminal of said subtractor is supplied with the replica signal from said digital-to-analog converter;

and

wherein the delay of said first variable delay circuit is variably controlled based on an output signal of said analog-to-digital converter to variably control the phase of said first clock signal.

10. The canceller circuit according to claim 3, further comprising

a timing controller, receiving a digital signal output at a frequency equal to the number of times of modulation per second (a baud rate) from said analog-to-digital converter, for controlling the delay time of said first and second variable delay circuits based on the received digital signal.

11. The canceller circuit according to claim 10, wherein

said timing controller variably controls the delay of said first and/or second variable delay circuits to maximize the power of said digital signal based on the digital signal from said analog-to-digital converter.

14. A canceller circuit comprising:

a subtractor for subtracting a replica signal of echo/crosstalk from a received signal;

an analog-to-digital converter for converting an analog signal output from said subtractor to a digital form;

an adaptive filter for receiving an output signal from said analog-to-digital converter and an input echo/crosstalk reference signal and for outputting a replica signal of the echo/crosstalk in a digital form; and

a digital-to-analog converter for receiving and converting a digital signal output from said adaptive filter to an analog form and for supplying a converted analog signal to said subtractor as said replica signal of echo/crosstalk;

said canceller circuit further comprising a control circuit for variably controlling the sampling phase in said digital-to-analog converter so that the phase of the replica signal of said echo/crosstalk output from said digital-to-analog converter is brought into coincidence with the phase of echo/crosstalk received by the subtractor.

15. A controlling method for a canceller circuit including a subtractor ahead of an analog-to-digital converter for converting an analog signal to a digital signal, said subtractor performing subtraction on an input received signal and a replica signal of echo/crosstalk in a continuous time analog domain;

an adaptive filter for outputting a replica signal of echo/crosstalk, as a digital signal, based on an input echo/crosstalk reference signal and an output signal of said analog-to-digital converter; and

a digital-to-analog converter supplied with the digital signal output from said adaptive filter to convert the digital signal to an analog signal to supply the analog signal to said subtractor as the replica signal of said echo/crosstalk;

said method comprising

a step of variably controlling the sampling phase in said digital-to-analog converter independently of the sampling phase on the side of said analog-to-digital converter; and

a step of controlling the phase of the signal waveform of the replica signal of said echo/crosstalk, output from said digital-to-analog converter, into coincidence with the phase of the echo/crosstalk received.

16. A controlling method for a canceller circuit in which

a subtractor for performing subtraction on a received signal and a replica signal of echo/crosstalk in a continuous time analog domain is provided in a pre-stage of an analog-to-digital converter adapted for converting an analog signal to a digital signal;

an output signal from an adaptive filter for outputting a filtered output as a digital signal, is carried by a sampling clock signal interchanged from a first sampling clock signal on the side of said analog-to-digital converter to a second sampling clock signal on the side of said digital-to-analog converter, based on an input echo/crosstalk reference signal and an output signal of said analog-to-digital converter, said output signal of the adaptive filter thus carried being input to said digital-to-analog converter and thereby converted to an analog signal which is output as said replica signal to said subtractor;

the phase of said second sampling clock signal on the side of said digital-to-analog converter being variably controlled independently of the phase of said first sampling clock signal on the side of said analog-to-digital converter;

said method comprising, in effecting training for phase control, the steps of

(a) in such a state where said echo/crosstalk reference signal is not supplied to said adaptive filter, the received signal from the counterpart device is not supplied to said subtractor and said replica signal from said digital-to-analog converter is not supplied,

supplying a signal formed only by echo/crosstalk to said subtractor, variably controlling the phase of said first sampling clock signal, based on an output signal of said analog-to-digital converter, and detecting a sampling position of said echo/crosstalk in said analog-to-digital converter;

(b) in a state where said subtractor is in a signal-less state, with there being no received signal from said counterpart device nor said echo/crosstalk, said echo/crosstalk reference signal is supplied to said adaptive filter, and where the replica signal from the digital-to-analog converter is supplied to said subtractor,

variably controlling the phase of said second sampling clock signal, based on an output signal of said analog-to-digital converter, so that, in said first sampling position of said analog-to-digital converter, the phase of the replica signal from the analog-to-digital converter will be coincident with the phase of the echo/crosstalk received; and

(c) not controlling and leaving unattended the phase of said first and second sampling clock signals, supplying the echo/crosstalk and said replica signal to the subtractor, supplying said analog-to-digital converter with a difference signal of said echo/crosstalk and said replica signal, output from said subtractor; and

supplying said adaptive filter with an output signal of said analog-to-digital converter as an error and with said echo/crosstalk reference signal as an input signal, and adaptively varying the filter coefficients for decreasing an error between a filter output signal and the echo/crosstalk as a target signal, to effect equalization pull-in to cancel the echo/crosstalk from an output of said subtractor.

17. The controlling method for a canceller circuit according to claim 16, further comprising the step of

in a normal operating mode following the training mode for phase control, supplying a received signal containing the echo/crosstalk to the first input terminal of said subtractor, supplying said adaptive filter with said echo/crosstalk reference signal, supplying said second input terminal of said subtractor with the replica signal from said digital-to-analog converter, and controlling the phase of said first sampling clock signal based on an output signal of said analog-to-digital converter.

18. The controlling method for a canceller circuit according to claim 16, wherein the frequency of said first and second sampling clock signals is equal to the number of times of modulation per second, that is a baud rate.