Method and system for hermetically sealing packages for optics

• US 20050101059A1
• Filed: 10/24/2003
• Published: 05/12/2005
• Est. Priority Date: 10/24/2003
• Status: Active Grant

• Current Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Original Assignee: XHP Microsystems, Inc.
• Inventors: Yang, Xiao
• Granted Patent: US 7,303,645 B2
• Time in Patent Office: Days
• US Class Current: 438/127
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: Y10T 156/1092 : All laminae planar and face to face
• CPC Class Codes: Y10T 156/1093 : with covering of discrete laminae with additional lamina

Abstract

A method for hermetically sealing devices. The method includes providing a substrate which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The method also provides a transparent member of a predetermined thickness which includes a plurality of recessed regions arranged in a spatial manner as a second array and a standoff region. The method also includes aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. The method further includes hermetically sealing each of the chips within one of the respective recessed regions by using at least a bonding process to isolate each of the chips within one of the recessed regions.

Claims

1. A method for hermetically sealing devices, the method comprising:

providing a substrate, the substrate including a plurality of individual chips, each of the chips including a plurality of devices, each of the chips being arranged in a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration;

providing a transparent member of a predetermined thickness, the transparent member including a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array, each of the recessed regions being bordered by a standoff region, the standoff region having a thickness defined by a portion of the predetermined thickness;

aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips whereupon the standoff region being coupled to each of the plurality of first street regions and being coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions; and

hermetically sealing each of the chips within one of the respective recessed regions by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

2. The method of claim 1 wherein each of the first street regions has a first width ranging from about 0.5 mm to 1.0 mm in dimension and each of the second street regions has a second width ranging from about 0.5 mm to 1.0 mm in dimension.

3. The method of claim 1 wherein the transparent member has an optical power transmittance of greater than about 99%.

4. The method of claim 1 wherein the transparent member is characterized by a coefficient of thermal expansion α

_T, the coefficient of thermal expansion is about the same as a coefficient of thermal expansion α

_S of the substrate.

5. The method of claim 1 wherein the transparent member comprises an antireflective coating disposed overlying surface regions of each of the recessed regions.

6. The method of claim 1 wherein each of the recessed regions is formed by a process selected from dry or wet etching, laser machining, acoustic machining, and casting.

7. The method of claim 1 wherein the transparent member comprises a first transparent member overlying a standoff layer, the standoff layer including the standoff region.

8. The method of claim 1 wherein the standoff layer comprises a second transparent member.

9. The method of claim 1 wherein the bonding process is selected from at least a plasma activated bonding, eutectic bonding, glue layer or adhesive bonding, welding, anodic bonding, and fusion bonding.

10. The method of claim 1 wherein the transparent member is characterized by a thickness ranging from about 0.1 mm to 1.2 mm.

11. The method of claim 1 wherein each of the chips is maintained within an inert environment within one of the respective recessed regions.

12. The method of claim 11 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.

13. The method of claim 12 wherein the inert environment causes a damping process.

14. The method of claim 12 wherein the inert environment causes a reduction in electrical breakdown.

15. The method of claim 1 wherein each of the chips comprises an interconnect region, the interconnect region being outside of the recessed region.

16. The method of claim 15 wherein the interconnect region is exposed through a through hole region on the transparent member.

17. The method of claim 16 wherein the interconnect region comprises a plurality of bonding pads.

18. The method of claim 1 wherein the substrate comprises a silicon bearing material.

19. The method of claim 18 wherein the substrate is a silicon wafer.

20. The method of claim 1 wherein each of the recessed regions comprises a first surface region coupled to a second surface region, the first surface region and the second surface region characterized to be of optical quality.

21. The method of claim 20 wherein the first surface region has a root mean square surface roughness of less than or equal to 2 Å

for a 2 μ

m by 2 μ

m area.

22. The method of claim 1 wherein each of the recessed regions is annular in shape.

23. The method of claim 1 wherein each of the recess regions has a depth of about 0.5 mm and less.

24. The method of claim 1 wherein the transparent member comprises a first side and a second side, the first side being parallel to the second side, the first side and the second side being coated with an antireflective material.

25. The method of claim 24 wherein the coating of antireflective material reduces the reflectance of visible light at the first side and the second side to less than 2% per side.

26. The method of claim 24 wherein the antireflective material comprises MgF₂.

27. The method of claim 1 further comprising:

dicing at least one of the chips by scribing a portion of each of the first street regions and by scribing a portion of each of the second street regions;

attaching at least one of the chips within one of the respective recessed regions to a lead frame structure;

wire bonding a portion of the attached chip to a portion of the lead frame structure; and

encapsulating the wire bonded portion of the attached chip and the portion of the lead frame structure while maintaining a surface region of the transparent substrate defined on the recessed region free of encapsulant.

28. The method of claim 1 wherein each of the recessed regions has a peripheral region that filters out light.

29. The method of claim 1 wherein each of the recessed regions has a peripheral region that forms an aperture region overlying a portion of one of the respective chips.

30. The method of claim 1 wherein at least one of the plurality of devices comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality of sensing devices, and an integrated circuit device.

60. The system of claim 3 wherein at least one of the plurality of devices comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality of sensing devices, and an integrated circuit device.

31. A system for hermetically sealing devices, the system comprising:

a substrate, the substrate configured to include a plurality of individual chips, wherein each of the chips includes a plurality of devices;

wherein each of the chips are arranged in a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street regions intersecting the first street regions to form the array configuration;

a transparent member of a predetermined thickness, the transparent member configured to include a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array, and wherein each of the recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness;

wherein the substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips, whereupon the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions; and

wherein each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

32. The system of claim 31 wherein each of the first street regions has a first width ranging from about 0.5 mm to 1.0 mm in dimension and each of the second street regions has a second width ranging from about 0.5 mm to 1.0 mm in dimension.

33. The system of claim 31 wherein the transparent member has an optical power transmittance of greater than about 99%.

34. The system of claim 31 wherein the transparent member is characterized by a coefficient of thermal expansion aT, the coefficient of thermal expansion is about the same as a coefficient of thermal expansion as of the substrate.

35. The system of claim 31 wherein the transparent member comprises an antireflective coating disposed overlying surface regions of each of the recessed regions.

36. The system of claim 31 wherein each of the recessed regions is formed by a process selected from dry or wet etching, laser machining, acoustic machining, and casting.

37. The system of claim 31 wherein the transparent member comprises a first transparent member overlying a standoff layer, the standoff layer including the standoff region.

38. The system of claim 31 wherein the standoff layer comprises a second transparent member.

39. The system of claim 31 wherein the bonding process is selected from at least a plasma activated bonding, eutectic bonding, glue layer or adhesive bonding, welding, anodic bonding, and fusion bonding.

40. The system of claim 31 wherein the transparent member is characterized by a thickness ranging from about 0.1 mm to 1.2 mm.

41. The system of claim 31 wherein each of the chips is maintained within an inert environment within one of the respective recessed regions.

42. The system of claim 41 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.

43. The system of claim 42 wherein the inert environment causes a damping process.

44. The system of claim 42 wherein the inert environment causes a reduction in electrical breakdown.

45. The system of claim 31 wherein each of the chips comprises an interconnect region, the interconnect region being outside of the recessed region.

46. The system of claim 45 wherein the interconnect region is exposed through a through hole region on the transparent member.

47. The system of claim 46 wherein the interconnect region comprises a plurality of bonding pads.

48. The system of claim 31 wherein the substrate comprises a silicon bearing material.

49. The system of claim 48 wherein the substrate is a silicon wafer.

50. The system of claim 31 wherein each of the recessed regions comprises a first surface region coupled to a second surface region, the first surface region and the second surface region characterized to be of optical quality.

51. The system of claim 50 wherein the first surface region has a root mean square surface roughness of less than or equal to 2 Å

for a 2 μ

m by 2 μ

m area.

52. The system of claim 31 wherein each of the recessed regions is annular in shape.

53. The system of claim 31 wherein each of the recess regions has a depth of about 0.5 mm and less.

54. The system of claim 31 wherein the transparent member comprises a first side and a second side, the first side being parallel to the second side, the first side and the second side being coated with an antireflective material.

55. The system of claim 54 wherein the coating of antireflective material reduces the reflectance of visible light at the first side and the second side to less than 2% per side.

56. The system of claim 54 wherein the antireflective material comprises MgF₂.

57. The system of claim 31 further comprising:

a lead frame structure;

wherein at least one of the chips is diced by scribing a portion of each of the first street regions and by scribing a portion of each of the second street regions, wherein at least one of the chips within one of the respective recessed regions is attached to the lead frame structure;

wherein a portion of the attached chip is wire bonded to a portion of the lead frame structure; and

wherein the wire bonded portion of the attached chip and the portion of the lead frame structure is encapsulated while maintaining a surface region of the transparent substrate defined on the recessed region free of encapsulant.

58. The system of claim 31 wherein each of the recessed regions has a peripheral region that filters out light.

59. The system of claim 31 wherein each of the recessed regions has a peripheral region that forms an aperture region overlying a portion of one of the respective chips.