Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells
First Claim
1. A method for manufacturing an integrated circuit memory device comprising:
- providing a programmable memory array of passive element memory cells, each memory cell comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of X-lines, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of Y-lines, said first semiconductor region being more lightly doped than the second semiconductor region; and
providing array support circuitry configured for impressing a programming pulse on a selected X-line and a programming pulse on a first selected Y-line;
wherein the selected X-line is pulsed from an unselected X-line bias voltage to a selected X-line bias voltage, and the first selected Y-line is pulsed from an unselected Y-line bias voltage to a selected Y-line bias voltage; and
wherein the first selected Y-line pulse substantially falls within the selected X-line pulse.
5 Assignments
0 Petitions
Accused Products
Abstract
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
61 Citations
25 Claims
-
1. A method for manufacturing an integrated circuit memory device comprising:
-
providing a programmable memory array of passive element memory cells, each memory cell comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of X-lines, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of Y-lines, said first semiconductor region being more lightly doped than the second semiconductor region; and
providing array support circuitry configured for impressing a programming pulse on a selected X-line and a programming pulse on a first selected Y-line;
wherein the selected X-line is pulsed from an unselected X-line bias voltage to a selected X-line bias voltage, and the first selected Y-line is pulsed from an unselected Y-line bias voltage to a selected Y-line bias voltage; and
wherein the first selected Y-line pulse substantially falls within the selected X-line pulse. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
-
Specification