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Control logic simulation-verification method and simulation-verification personal computer

  • US 20050102126A1
  • Filed: 09/30/2003
  • Published: 05/12/2005
  • Est. Priority Date: 10/10/2002
  • Status: Abandoned Application
First Claim
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1. A control logic simulation-verification method, comprising:

  • executing a control logic and a plant model logic on a reconfigurable identical operating system, said control logic being adapted to output, in accordance with an operating status, a control command signal necessary for exercising run control of a plant, said plant model logic being adapted to perform a simulated action, simulating an action status of the plant, upon receipt of said control command signal, and output a run status signal showing the action status, and said operating system being usable as a combination of only necessary functional portions.

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