High temperature memory device

• US 20050104104A1
• Filed: 11/18/2004
• Published: 05/19/2005
• Est. Priority Date: 11/18/2003
• Status: Abandoned Application

• Current Assignee: Halliburton Energy Services Incorporated (Halliburton Company)
• Original Assignee: Halliburton Energy Services Incorporated (Halliburton Company)
• Inventors: Schultz, Roger L., Freeman, James J.
• Application Number:
  US10/992,144
• Publication Number:
  US 20050104104A1
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 21/8213 the substrate being a semiconductor, using SiC technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it.

Claims

1. A high temperature nonvolatile integrated device, comprising:

a substrate comprising at least one of sapphire and spinel; and

a plurality of ferroelectric memory cells disposed on the substrate.

2. The device of claim 1, wherein the plurality of ferroelectric memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

3. The device of claim 2, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a ferroelectric memory element, said ferroelectric memory element made accessible by the assertion of a row line.

4. The device of claim 1, wherein each ferroelectric memory cell includes an island of semiconducting material containing only one transistor.

5. A high temperature nonvolatile integrated device that comprises:

a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer; and

a plurality of ferroelectric memory cells disposed on the substrate.

6. The device of claim 5, wherein the plurality of ferroelectric memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

7. The device of claim 6, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a ferroelectric memory element, said ferroelectric memory element made accessible by the assertion of a row line.

8. The device of claim 5, wherein each ferroelectric memory cell includes an island of semiconducting material containing only one transistor.

9. A high temperature nonvolatile integrated device, comprising:

a large-bandgap semiconductor substrate; and

a plurality of ferroelectric memory cells disposed on the substrate.

10. The device of claim 9, wherein the plurality of ferroelectric cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

11. The device of claim 10, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a ferroelectric memory element, said ferroelectric memory element made accessible by the assertion of a row line.

12. The device of claim 11, wherein the large bandgap semiconductor comprises silicon carbide (SiC).

13. The device of claim 11, wherein the large bandgap semiconductor comprises gallium arsenide (GaAs).

14. A high temperature nonvolatile integrated device that comprises:

a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer; and

a plurality of magnetic memory cells disposed on the substrate.

15. The device of claim 14, wherein the plurality of magnetic memory cells are coupled to form a random access memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

16. The device of claim 15, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a magnetic memory element made accessible by the assertion of a row line.

17. The device of claim 14, wherein each magnetic memory cell includes an island of semiconducting material containing only one transistor.

18. The device of claim 14, wherein each magnetic memory cell includes a magnetic tunnel junction (MTJ).

19. The device of claim 14, wherein each magnetic memory cell includes a giant magnetoresistive effect (GMR) element.

20. A high temperature nonvolatile integrated device that comprises:

a large bandgap semiconductor substrate; and

a plurality of magnetic memory cells disposed on the substrate.

21. The device of claim 20, wherein the plurality of magnetic memory cells are coupled to form a random access memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

22. The device of claim 21, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a magnetic memory element made accessible by the assertion of a row line.

23. The device of claim 22, wherein the large bandgap semiconductor comprises silicon carbide (SiC).

24. The device of claim 22, wherein the large bandgap semiconductor comprises gallium arsenide (GaAs).

25. The device of claim 20, wherein each magnetic memory cell includes a magnetic tunnel junction (MTJ).

26. The device of claim 20, wherein each magnetic memory cell includes a giant magnetoresistive effect (GMR) element.

27. A high temperature non-volatile memory, comprising

a silicon carbide integrated circuit substrate;

a plurality of magnetic random access memory (MRAM) cells disposed on the silicon carbide substrate; and

silicon carbide electronic circuits for operating the plurality of MRAM cells, the silicon carbide electronic circuits disposed on the silicon carbide substrate.

28. A high temperature electrically erasable and programmable device that comprises:

a sapphire or spinel substrate; and

a plurality of memory cells disposed on the substrate, each memory cell including a floating gate transistor.

29. The device of claim 28, wherein the plurality of memory cells are coupled to form a memory cell array, and wherein the memory further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

30. The device of claim 29, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a detector module to apply an electric field across a memory element made accessible by the assertion of a row line.

31. The device of claim 28, wherein each memory cell includes an island of semiconducting material containing only one transistor.

32. The device of claim 29, wherein the device is configured as a Flash memory.

33. A high temperature electrically erasable and programmable device that comprises:

a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer;

a plurality of memory cells disposed on the substrate, each memory cell including a floating gate transistor.

34. The device of claim 33, wherein the plurality of memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

35. The device of claim 34, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a memory element made accessible by the assertion of a row line.

36. The device of claim 33, wherein each memory cell includes an island of semiconducting material containing only one transistor.

37. The device of claim 34, wherein the support circuitry is configured to erase a bank of data words in one operation.

38. A high temperature electrically erasable and programmable memory that comprises:

a large-bandgap semiconductor substrate; and

a plurality of memory cells disposed on the substrate, each memory cell including a floating gate transistor.

39. The memory of claim 38, wherein the plurality of memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read and store data.

40. The memory of claim 39, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a driver/detector module to apply an electric field across a memory element made accessible by the assertion of a row line.

41. The memory of claim 40, wherein the large bandgap semiconductor comprises silicon carbide (SiC).

42. The memory of claim 40, wherein the large bandgap semiconductor comprises gallium arsenide (GaAs).

43. The memory of claim 39, wherein the device is configured to erase multiple rows of memory cells concurrently.

44. A high temperature electrically erasable and programmable read only memory (EEPROM), comprising:

a silicon carbide substrate;

a plurality of memory cells disposed on the silicon carbide substrate;

a silicon carbide charge pump circuit disposed on the silicon carbide substrate; and

electronic circuits for operating the plurality of memory cells, the silicon carbide electronic circuits disposed on the silicon carbide substrate.

45. The memory of claim 44, wherein the memory is configured as a Flash memory.

46. The memory of claim 44, wherein the plurality of memory cells are coupled in parallel to form a composite memory cell.

47. The memory of claim 44, wherein the plurality of memory cells are coupled in series to form a composite memory cell.

48. A high temperature nonvolatile integrated device that comprises:

a sapphire or spinel substrate; and

a plurality of memory cells disposed on the substrate, each memory cell including a fuse or antifuse element.

49. The device of claim 48, wherein the plurality of memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read data.

50. The device of claim 49, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a detector module to apply an electric field across a fuse or antifuse element made accessible by the assertion of a row line.

51. The device of claim 48, wherein each memory cell includes an island of semiconducting material containing only one diode.

52. A high temperature nonvolatile integrated device that comprises:

a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer;

a plurality of memory cells disposed on the substrate, each memory cell including a fuse or antifuse element.

53. The device of claim 52, wherein the plurality of memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read data.

54. The device of claim 53, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a detector module to apply an electric field across a fuse or antifuse element made accessible by the assertion of a row line.

55. The device of claim 52, wherein each memory cell includes an island of semiconducting material containing no more than one diode.

56. A high temperature nonvolatile integrated device, comprising:

a large-bandgap semiconductor substrate; and

a plurality of memory cells disposed on the substrate, each memory cell including a fuse or antifuse element.

57. The device of claim 56, wherein the plurality of memory cells are coupled to form a memory cell array, and wherein the device further comprises support circuitry disposed on the substrate to selectively access cells in the memory array to read data.

58. The device of claim 57, wherein the support circuitry includes:

a row decoder to assert, in response to an address value, a corresponding row line; and

a detector module to apply an electric field across a fuse or antifuse element made accessible by the assertion of a row line.

59. The device of claim 58, wherein the large bandgap semiconductor comprises silicon carbide (SiC).

60. The device of claim 58, wherein the large bandgap semiconductor comprises gallium arsenide (GaAs).

61. A robust memory device that comprises:

a plurality of composite memory cells coupled to form a memory cell array; and

support circuitry to selectively access composite memory cells in the memory array to read and store data.

62. The device of claim 61, wherein each composite memory cell comprises two or more component memory cells coupled in parallel to operate concurrently when the composite memory cell is selected.

63. The device of claim 62, wherein each component memory cell comprises a ferroelectric memory element.

64. The device of claim 61, wherein each composite memory cell comprises two or more component memory cells coupled in series to operate concurrently when the composite memory cell is selected.

65. The device of claim 64, wherein each component memory cell comprises a magnetoresistive memory element.

66. The device of claim 64, wherein each component memory cell comprises a floating gate transistor.