High temperature memory device
First Claim
1. A high temperature nonvolatile integrated device, comprising:
- a substrate comprising at least one of sapphire and spinel; and
a plurality of ferroelectric memory cells disposed on the substrate.
1 Assignment
0 Petitions
Accused Products
Abstract
Disclosed herein are various nonvolatile integrated device embodiments suitable for use at high temperatures. In some embodiments, a high temperature nonvolatile integrated device comprises a sapphire or spinel substrate having multiple ferroelectric memory cells disposed upon it. In other embodiments, a high temperature nonvolatile integrated device comprises a silicon on insulator substrate or a large bandgap semiconductor substrate having multiple ferroelectric or magnetic memory cells disposed on it. In yet other embodiments, a high temperature nonvolatile integrated device comprises a sapphire, silicon on insulator, or a large bandgap substrate having programmable read only memory (PROM) cells or electrically erasable PROM (EEPROM) cells disposed on it.
-
Citations
66 Claims
-
1. A high temperature nonvolatile integrated device, comprising:
-
a substrate comprising at least one of sapphire and spinel; and
a plurality of ferroelectric memory cells disposed on the substrate. - View Dependent Claims (2, 3, 4)
-
-
5. A high temperature nonvolatile integrated device that comprises:
-
a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer; and
a plurality of ferroelectric memory cells disposed on the substrate. - View Dependent Claims (6, 7, 8)
-
-
9. A high temperature nonvolatile integrated device, comprising:
-
a large-bandgap semiconductor substrate; and
a plurality of ferroelectric memory cells disposed on the substrate. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A high temperature nonvolatile integrated device that comprises:
-
a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer; and
a plurality of magnetic memory cells disposed on the substrate. - View Dependent Claims (15, 16, 17, 18, 19)
-
-
20. A high temperature nonvolatile integrated device that comprises:
-
a large bandgap semiconductor substrate; and
a plurality of magnetic memory cells disposed on the substrate. - View Dependent Claims (21, 22, 23, 24, 25, 26)
-
-
27. A high temperature non-volatile memory, comprising
a silicon carbide integrated circuit substrate; -
a plurality of magnetic random access memory (MRAM) cells disposed on the silicon carbide substrate; and
silicon carbide electronic circuits for operating the plurality of MRAM cells, the silicon carbide electronic circuits disposed on the silicon carbide substrate.
-
-
28. A high temperature electrically erasable and programmable device that comprises:
-
a sapphire or spinel substrate; and
a plurality of memory cells disposed on the substrate, each memory cell including a floating gate transistor. - View Dependent Claims (29, 30, 31, 32)
-
-
33. A high temperature electrically erasable and programmable device that comprises:
-
a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer;
a plurality of memory cells disposed on the substrate, each memory cell including a floating gate transistor. - View Dependent Claims (34, 35, 36, 37)
-
-
38. A high temperature electrically erasable and programmable memory that comprises:
-
a large-bandgap semiconductor substrate; and
a plurality of memory cells disposed on the substrate, each memory cell including a floating gate transistor. - View Dependent Claims (39, 40, 41, 42, 43)
-
-
44. A high temperature electrically erasable and programmable read only memory (EEPROM), comprising:
-
a silicon carbide substrate;
a plurality of memory cells disposed on the silicon carbide substrate;
a silicon carbide charge pump circuit disposed on the silicon carbide substrate; and
electronic circuits for operating the plurality of memory cells, the silicon carbide electronic circuits disposed on the silicon carbide substrate. - View Dependent Claims (45, 46, 47)
-
-
48. A high temperature nonvolatile integrated device that comprises:
-
a sapphire or spinel substrate; and
a plurality of memory cells disposed on the substrate, each memory cell including a fuse or antifuse element. - View Dependent Claims (49, 50, 51)
-
-
52. A high temperature nonvolatile integrated device that comprises:
-
a bulk silicon substrate having a silicon surface layer separated from the bulk silicon by an insulating layer;
a plurality of memory cells disposed on the substrate, each memory cell including a fuse or antifuse element. - View Dependent Claims (53, 54, 55)
-
-
56. A high temperature nonvolatile integrated device, comprising:
-
a large-bandgap semiconductor substrate; and
a plurality of memory cells disposed on the substrate, each memory cell including a fuse or antifuse element. - View Dependent Claims (57, 58, 59, 60)
-
-
61. A robust memory device that comprises:
-
a plurality of composite memory cells coupled to form a memory cell array; and
support circuitry to selectively access composite memory cells in the memory array to read and store data. - View Dependent Claims (62, 63, 64, 65, 66)
-
Specification