Method of fabricating a high-voltage transistor with an extended drain structure
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Abstract
A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
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Citations
42 Claims
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1. -33. (canceled)
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34. A method for fabricating a high-voltage transistor comprising:
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forming, in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls;
partially filling each of the trenches with a dielectric material that covers the first and second sidewalls;
filling a remaining portion of the trenches with a conductive material to form first and second field plates in the first and second trenches, respectively;
forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the mesa, the lower portion of the mesa comprising a drift region. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42)
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Specification