Methods and apparatus for packaging integrated circuit devices

• US 20050104179A1
• Filed: 07/02/2004
• Published: 05/19/2005
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Shellcase Ltd. (Adeia Inc.)
• Inventors: Oganesian, Vage, Aksenton, Julia, Zilber, Gil
• Granted Patent: US 7,192,796 B2
• Time in Patent Office: Days
• US Class Current: 257/684
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 : Colour filter arrangements
• CPC Class Codes: H01L 27/14632 : Wafer-level processed structures
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14685 : Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 : Wafer level processing
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02327 : the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 33/385 : the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.

Claims

1. An integrally packaged optronic integrated circuit device comprising:

an integrated circuit die comprising;

a crystalline substrate having first and second generally planar surfaces and edge surfaces; and

optronic semiconductor circuitry formed over said first generally planar surface;

at least one chip scale packaging layer formed over said semiconductor circuitry and said first generally planar surface; and

at least one electrical conductor overlying said second generally planar surface, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface.

2. An integrally packaged integrated circuit device according to claim 1 and wherein said at least one chip scale packaging layer is formed of at least one of glass, quartz and sapphire.

3. An integrally packaged optronic integrated circuit device according to claim 1 and also comprising an insulation layer formed over said second generally planar surface and said edge surfaces and underlying said at least one electrical conductor.

4. An integrally packaged optronic integrated circuit device according to claim 3 and wherein said insulation layer comprises a mechanically conforming layer.

5. An integrally packaged optronic integrated circuit device according to claim 1 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends generally parallel to and in touching electrical engagement with a planar surface of said at least one pad.

6. An integrally packaged optronic integrated circuit device according to claim 1 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends in touching electrical engagement with an edge of said at least one pad.

7. An integrally packaged optronic integrated circuit device according to claim 1 and wherein said at least one chip scale packaging layer is adhered to said first generally planar surface by a bonding layer.

8. An integrally packaged optronic integrated circuit device according to claim 7 and wherein said bonding layer has spectral filter functionality.

9. An integrally packaged optronic integrated circuit device according to claim 1 and also including at least one spectral filter associated with at least a portion of a radiation transparent protective surface.

10. An integrally packaged optronic integrated circuit device according to claim 9 and wherein said radiation transparent protective surface comprises at least one of a top surface and an edge surface.

11. An integrally packaged optronic integrated circuit device according to claim 1 and also including color array filters.

12. An integrally packaged optronic integrated circuit device according to claim 1 and also comprising at least one lens integrally formed on a transparent protective surface thereof.

13. An integrally packaged optronic integrated circuit device according to claim 1 and wherein said at least one chip scale packaging layer comprises at least one lens.

14. An integrally packaged optronic integrated circuit device according to claim 12 and wherein said at least one lens is maintained at a precisely fixed distance with respect to said optronic semiconductor circuitry.

15. An integrally packaged optronic integrated circuit device according to claim 13 and wherein said at least one lens is maintained at a precisely fixed distance with respect to said optronic semiconductor circuitry.

16. An integrally packaged optronic integrated circuit device according to claim 1 and also including light coupling bumps formed on a transparent protective surface thereof.

17. An integrally packaged optronic integrated circuit device according to claim 1 and also including a waveguide and other optical components formed on a transparent protective surface thereof.

18. An integrally packaged optronic integrated circuit device according to claim 1 and also including an optical grating formed onto a transparent protective surface thereof.

19. An integrally packaged optronic integrated circuit device according to claim 1 and also including a polarizer integrated therewith.

20. An integrally packaged optronic integrated circuit device according to claim 1 and also including a trench formed between different elements on the integrated circuit die.

21. An integrally packaged optronic integrated circuit device according to claim 1 and wherein said crystalline substrate and said at least one packaging layer define at least one gap therebetween.

22. An integrally packaged optronic integrated circuit device according to claim 21 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends generally parallel to and in touching electrical engagement with a planar surface of said at least one pad.

23. An integrally packaged optronic integrated circuit device according to claim 21 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends in touching electrical engagement with an edge of said at least one pad.

24. An integrally packaged optronic integrated circuit device according to claim 21 and also including at least one spectral filter associated with a radiation transparent protective surface.

25. An integrally packaged optronic integrated circuit device according to claim 21 and also including color array filters.

26. An integrally packaged optronic integrated circuit device according to claim 21 and also having at least one lens integrally formed on a transparent protective surface thereof.

27. An integrally packaged optronic integrated circuit device according to claim 21 and also including light coupling bumps formed on a transparent protective surface thereof.

28. An integrally packaged optronic integrated circuit device according to claim 21 and also including a waveguide and other optical components integrally formed on a transparent protective surface thereof.

29. An integrally packaged optronic integrated circuit device according to claim 21 and also including an optical grating formed onto a transparent protective surface thereof.

30. An integrally packaged optronic integrated circuit device according to claim 21 and also including a polarizer integrated therewith.

31. An integrally packaged optronic integrated circuit device according to claim 21 and also including a trench formed between different elements on the integrated circuit die.

32. An integrally packaged optronic integrated circuit device comprising:

an integrated circuit die comprising;

a crystalline substrate having first and second generally planar surfaces and edge surfaces; and

optronic semiconductor circuitry formed over said first generally planar surface;

at least one chip scale packaging layer formed over said semiconductor circuitry and said first generally planar surface; and

at least one electrical conductor overlying at least one of said edge surfaces, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface.

33. An integrally packaged integrated circuit device according to claim 32 and wherein said at least one chip scale packaging layer is formed of at least one of glass, quartz and sapphire.

34. An integrally packaged optronic integrated circuit device according to claim 32 and also comprising an insulation layer formed over said second generally planar surface and said edge surfaces and underlying said at least one electrical conductor.

35. An integrally packaged optronic integrated circuit device according to claim 34 and wherein said insulation layer comprises a mechanically conforming layer.

36. An integrally packaged optronic integrated circuit device according to claim 32 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends generally parallel to and in touching electrical engagement with a planar surface of said at least one pad.

37. An integrally packaged optronic integrated circuit device according to claim 32 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends in touching electrical engagement with an edge of said at least one pad.

38. An integrally packaged optronic integrated circuit device according to claim 32 and wherein said at least one chip scale packaging layer is adhered to said first generally planar surface by a bonding layer.

39. An integrally packaged optronic integrated circuit device according to claim 38 and wherein said bonding layer has spectral filter functionality.

40. An integrally packaged optronic integrated circuit device according to claim 32 and also including at least one spectral filter associated with at least a portion of a radiation transparent protective surface.

41. An integrally packaged optronic integrated circuit device according to claim 40 and wherein said radiation transparent protective surface comprises at least one of a top surface and an edge surface.

42. An integrally packaged optronic integrated circuit device according to claim 32 and also including color array filters.

43. An integrally packaged optronic integrated circuit device according to claim 32 and also comprising at least one lens integrally formed on a transparent protective surface thereof.

44. An integrally packaged optronic integrated circuit device according to claim 32 and wherein said at least one chip scale packaging layer comprises at least one lens.

45. An integrally packaged optronic integrated circuit device according to claim 43 and wherein said at least one lens is maintained at a precisely fixed distance with respect to said optronic semiconductor circuitry.

46. An integrally packaged optronic integrated circuit device according to claim 44 and wherein said at least one lens is maintained at a precisely fixed distance with respect to said optronic semiconductor circuitry.

47. An integrally packaged optronic integrated circuit device according to claim 32 and also including light coupling bumps formed on a transparent protective surface thereof.

48. An integrally packaged optronic integrated circuit device according to claim 32 and also including a waveguide and other optical components formed on a transparent protective surface thereof.

49. An integrally packaged optronic integrated circuit device according to claim 32 and also including an optical grating formed onto a transparent protective surface thereof.

50. An integrally packaged optronic integrated circuit device according to claim 32 and also including a polarizer integrated therewith.

51. An integrally packaged optronic integrated circuit device according to claim 32 and also including a trench formed between different elements on the integrated circuit die.

52. An integrally packaged optronic integrated circuit device according to claim 32 and wherein said crystalline substrate and said at least one packaging layer define at least one gap therebetween.

53. An integrally packaged optronic integrated circuit device according to claim 52 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends generally parallel to and in touching electrical engagement with a planar surface of said at least one pad.

54. An integrally packaged optronic integrated circuit device according to claim 52 and wherein said at least one electrical conductor is connected to said at least one pad via a portion of said electrical conductor which extends in touching electrical engagement with an edge of said at least one pad.

55. An integrally packaged optronic integrated circuit device according to claim 52 and also including at least one spectral filter associated with a radiation transparent protective surface.

56. An integrally packaged optronic integrated circuit device according to claim 52 and also including color array filters.

57. An integrally packaged optronic integrated circuit device according to claim 52 and also having at least one lens integrally formed on a transparent protective surface thereof.

58. An integrally packaged optronic integrated circuit device according to claim 52 and also including light coupling bumps formed on a transparent protective surface thereof.

59. An integrally packaged optronic integrated circuit device according to claim 52 and also including a waveguide and other optical components integrally formed on a transparent protective surface thereof.

60. An integrally packaged optronic integrated circuit device according to claim 52 and also including an optical grating formed onto a transparent protective surface thereof.

61. An integrally packaged optronic integrated circuit device according to claim 52 and also including a polarizer integrated therewith.

62. An integrally packaged optronic integrated circuit device according to claim 52 and also including a trench formed between different elements on the integrated circuit die.

63. A method of producing integrally packaged optronic integrated circuit devices comprising:

providing a plurality of integrated circuit dies formed on a wafer having first and second generally planar surfaces and optronic semiconductor circuitry formed over said first generally planar surface;

forming at least one chip scale packaging layer over said semiconductor circuitry and said first generally planar surface;

separating said integrated circuit dies from each other along dice lines defined in said second generally planar surface, so as to define edge surfaces of said dies while said dies remain attached to said packaging layer;

forming at least one electrical conductor overlying said second generally planar surface, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface; and

subsequently dicing said wafer to define a plurality of packaged optronic integrated circuit devices.

64. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said at least one chip scale packaging layer is formed of at least one of glass, quartz and sapphire.

65. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 also comprising forming an insulation layer over said second generally planar surface and said edge surfaces and underlying said at least one electrical conductor.

66. A method of producing integrally packaged optronic integrated circuit devices according to claim 65 and wherein said insulation layer comprises a mechanically conforming layer.

67. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 wherein said forming at least one electrical conductor comprises forming a portion of said at least one electrical conductor generally parallel to and in touching electrical engagement with a planar surface of said at least one pad.

68. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 wherein said forming at least one electrical conductor comprises forming a portion of said at least one electrical conductor to be in touching electrical engagement with an edge of said at least one pad.

69. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 wherein said forming at least one chip scale packaging layer comprises adhering said at least one chip scale packaging layer to said first generally planar surface using a bonding layer.

70. A method of producing integrally packaged optronic integrated circuit devices according to claim 69 and wherein said bonding layer has spectral filter functionality.

71. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises forming at least one spectral filter on at least a portion of a radiation transparent protective surface of said chip scale packaging layer.

72. A method of producing integrally packaged optronic integrated circuit devices according to claim 71 and wherein said radiation transparent protective surface comprises at least one of a top surface and an edge surface.

73. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises forming color array filters on said chip scale packaging layer.

74. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises integrally forming at least one lens on a radiation transparent protective surface of said chip scale packaging layer.

75. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming at least one chip scale packaging layer comprises forming at least one lens.

76. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and also comprising integrally forming at least one lens on a radiation transparent protective surface of said chip scale packaging layer.

77. A method of producing integrally packaged optronic integrated circuit devices according to claim 74 and wherein said forming said at least one lens comprises maintaining said at least one lens at a precisely fixed distance with respect to said optronic semiconductor circuitry.

78. A method of producing integrally packaged optronic integrated circuit devices according to claim 75 and wherein said forming said at least one lens comprises maintaining said at least one lens at a precisely fixed distance with respect to said optronic semiconductor circuitry.

79. A method of producing integrally packaged optronic integrated circuit devices according to claim 76 and wherein said forming said at least one lens comprises maintaining said at least one lens at a precisely fixed distance with respect to said optronic semiconductor circuitry.

80. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises forming light coupling bumps on a radiation transparent protective surface of said chip scale packaging layer.

81. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises forming a waveguide and other optical components on a radiation transparent protective surface of said chip scale packaging layer.

82. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises forming an optical grating on a radiation transparent protective surface of said chip scale packaging layer.

83. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and wherein said forming said chip scale packaging layer also comprises integrally forming a polarizer thereon.

84. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and also comprising forming a trench between different elements on the integrated circuit die.

85. A method of producing integrally packaged optronic integrated circuit devices according to claim 63 and also comprising inserting a spacer element over said semiconductor circuitry and said first generally planar surface prior to said forming said chip scale packaging layer.

86. A method of producing integrally packaged optronic integrated circuit devices comprising:

providing a plurality of integrated circuit dies formed on a wafer having first and second generally planar surfaces and optronic semiconductor circuitry formed over said first generally planar surface;

forming at least one chip scale packaging layer over said semiconductor circuitry and said first generally planar surface;

separating said integrated circuit dies from each other along dice lines defined in said second generally planar surface, so as to define edge surfaces of said dies while said dies remain attached to said packaging layer;

forming at least one electrical conductor overlying at least one of said edge surfaces, said at least one electrical conductor being connected to said circuitry by at least one pad formed directly on said first generally planar surface; and

subsequently dicing said wafer to define a plurality of packaged optronic integrated circuit devices.

87. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said at least one chip scale packaging layer is formed of at least one of glass, quartz and sapphire.

88. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 also comprising forming an insulation layer over said second generally planar surface and said edge surfaces and underlying said at least one electrical conductor.

89. A method of producing integrally packaged optronic integrated circuit devices according to claim 88 and wherein said insulation layer comprises a mechanically conforming layer.

90. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 wherein said forming at least one electrical conductor comprises forming a portion of said at least one electrical conductor generally parallel to and in touching electrical engagement with a planar surface of said at least one pad.

91. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 wherein said forming at least one electrical conductor comprises forming a portion of said at least one electrical conductor to be in touching electrical engagement with an edge of said at least one pad.

92. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 wherein said forming at least one chip scale packaging layer comprises adhering said at least one chip scale packaging layer to said first generally planar surface using a bonding layer.

93. A method of producing integrally packaged optronic integrated circuit devices according to claim 92 and wherein said bonding layer has spectral filter functionality.

94. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises forming at least one spectral filter on at least a portion of a radiation transparent protective surface of said chip scale packaging layer.

95. A method of producing integrally packaged optronic integrated circuit devices according to claim 94 and wherein said radiation transparent protective surface comprises at least one of a top surface and an edge surface.

96. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises forming color array filters on said chip scale packaging layer.

97. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises integrally forming at least one lens on a radiation transparent protective surface of said chip scale packaging layer.

98. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming at least one chip scale packaging layer comprises forming at least one lens.

99. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and also comprising integrally forming at least one lens on a radiation transparent protective surface of said chip scale packaging layer.

100. A method of producing integrally packaged optronic integrated circuit devices according to claim 97 and wherein said forming said at least one lens comprises maintaining said at least one lens at a precisely fixed distance with respect to said optronic semiconductor circuitry.

101. A method of producing integrally packaged optronic integrated circuit devices according to claim 98 and wherein said forming said at least one lens comprises maintaining said at least one lens at a precisely fixed distance with respect to said optronic semiconductor circuitry.

102. A method of producing integrally packaged optronic integrated circuit devices according to claim 99 and wherein said forming said at least one lens comprises maintaining said at least one lens at a precisely fixed distance with respect to said optronic semiconductor circuitry.

103. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises forming light coupling bumps on a radiation transparent protective surface of said chip scale packaging layer.

104. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises forming a waveguide and other optical components on a radiation transparent protective surface of said chip scale packaging layer.

105. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises forming an optical grating on a radiation transparent protective surface of said chip scale packaging layer.

106. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and wherein said forming said chip scale packaging layer also comprises integrally forming a polarizer thereon.

107. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and also comprising forming a trench between different elements on the integrated circuit die.

108. A method of producing integrally packaged optronic integrated circuit devices according to claim 86 and also comprising inserting a spacer element over said semiconductor circuitry and said first generally planar surface prior to said forming said chip scale packaging layer.