AM data recovery circuit

• US 20050104572A1
• Filed: 12/02/2004
• Published: 05/19/2005
• Est. Priority Date: 04/09/2002
• Status: Active Grant

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: MStar Semiconductor Incorporated (MediaTek, Inc.)
• Inventors: Smith, Sterling, Tin-Hang Yung, Henry
• Granted Patent: US 7,702,043 B2
• Time in Patent Office: Days
• US Class Current: 323/304
• CPC Class Codes: G06K 19/0713 the arrangement including a power charge pump
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G11C 5/142 Contactless power supplies, e.g. RF, induction, or IR
• CPC Class Codes: H04B 5/0062 in RFID [Radio Frequency Identification] Systems
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: H04B 7/086 using weights depending on external parameters, e.g. direction of arrival [DOA], predetermined weights or beamforming
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention provides a passive RFID chip with on-chip charge pumps for generating electrical power for the chip from radio frequencies. The passive RFID chip comprises an analog portion and a digital portion. The analog portion primarily comprises a voltage sensor and an AM data detector. The digital portion comprises a state machine digital logic controller. Incoming RF signals enter the chip via external antennas. The RF signals are converted into regulated DC signals by RF-DC converters with the voltage sensor. The RF-DC converters provide power for all the on-chip components and hence the chip does not require external power supply. The incoming RF signals are demodulated by demodulators and enter the AM data detector where the envelope transitions are detected. A voltage alarm is provided to ensure the voltage level does not drop below an operational level of the chip. The logic signals and programming data are controlled by the state machine digital logic controller and the timing signals are provided by an on-chip oscillator.

Claims

1-8. -8. (canceled)

9. An AM data recovery circuit, comprising:

a demodulator for converting an incoming RF signal at an input mode to a base-band signal at an output node;

a low pass filter for generating a reference signal that follows and approaches said base-band signal with a time constant;

a comparator for comparing said base-band signal and said reference signal so as to generate a digital data signal;

a reset for generating a reset signal in response to transitions of said digital data signal; and

a switch for resetting said reference signal in response to said reset signal.

10. The AM data recovery circuit as claimed in claim 9, wherein said filter comprises:

a resistor connected to said output node of said demodulator; and

a capacitor connected to said resistor to form a reference signal node at which said reference signal can be generated.

11. The AM data recovery circuit as claimed in claim 10, wherein said switch is a MOS transistor connected to said resistor in parallel while said MOS transistor has a gate controlled by said reset signal.

12. The AM data recovery circuit as claimed in claim 9, wherein said comparator has hysteresis.

13. The AM data recovery circuit as claimed in claim 9, said demodulator has a plurality of series-connected stages, each of which comprises:

a first diode having an anode connected to an input terminal and a cathode connected to a central terminal;

a second diode having an anode connected to said central terminal and a cathode connected to an output terminal;

a first capacitor connected between said central terminal and said input node;

a second capacitor connected between said output terminal and a reference node; and

a third diode having an anode connected to said output terminal and a cathode connected to said output node.

14. The AM data recovery circuit as claimed in claim 13, wherein said first and second diodes are implemented by low threshold diode-connected MOS transistors.

15. The AM data recovery circuit as claimed in claim 13, wherein said first and second capacitors are implemented by metal-insulator-metal (MIM) capacitors.

16. The AM data recovery circuit as claimed in claim 13, wherein said demodulator further comprises a switch connected between said output terminal of the next last stage and said output node while said switch is controlled by said output terminal of the last stage.