Dynamic buffer pages

• US 20050104890A1
• Filed: 12/07/2004
• Published: 05/19/2005
• Est. Priority Date: 02/15/2001
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Champion, Mark
• Granted Patent: US 7,573,483 B2
• Time in Patent Office: Days
• US Class Current: 345/531
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2352/00 Parallel handling of streams of display data
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 3/001 using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background slide projectors per se G03B23/00 = 42 HP
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/7416 involving the use of a spatial light modulator, e.g. a light valve, controlled by a video signal
• CPC Class Codes: H04N 7/01 Conversion of standards , e.g. involving analogue television standards or digital television standards processed at pixel level
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Abstract

Methods and apparatus for adjusting the geometry of buffer pages. In one implementation, a buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order, where each data element corresponds to an entry in one of a plurality of buffer pages, each buffer page having a plurality of entries along a first dimension corresponding to the first order and a plurality of entries along a second dimension corresponding to the second order; at least one memory device, each memory device having a plurality of memory pages including a plurality of memory locations, each memory location having an address, where data elements are stored to each memory device in the first order and retrieved from each memory device in the second order, and where each memory page stores data elements in multiple locations according to the first order and stores data elements in multiple locations according to the second order; and a buffer page controller, where the buffer page controller controls the geometry of each buffer page.

Claims

1. A buffer page system, comprising:

a data source, providing data elements in a first order;

a data destination, receiving data elements in a second order, wherein each data element corresponds to an entry in one of a plurality of buffer pages, each buffer page having a plurality of entries along a first dimension and a plurality of entries along a second dimension; and

a buffer page controller, wherein the buffer page controller controls the geometry of each buffer page.

2. The buffer page system of claim 1, wherein:

a data element is pixel data corresponding to a pixel in a frame of pixels;

the buffer pages are pixel pages, each pixel page having a plurality of pixel page rows and a plurality of pixel page columns; and

the buffer page controller is a pixel page controller and controls a pixel page geometry for pixel pages.

3. The buffer page system of claim 2, wherein the pixel page controller selects a pixel page geometry from a group of two or more available pixel page geometries.

4. The buffer page system of claim 2, wherein the pixel page controller sets the pixel page geometry according to an instruction received from the data source.

5. The buffer page system of claim 2, wherein the pixel page controller sets the pixel page geometry based on one or more criteria.

6. The buffer page system of claim 5, wherein the data source provides one or more criteria to the pixel page controller.

7. The buffer page system of claim 5, wherein one criterion is reducing page misses.

8. The buffer page system of claim 5, wherein one criterion is reducing effective page misses.

9. The buffer page system of claim 5, wherein one criterion is maximizing an output data rate.

10. The buffer page system of claim 5, wherein one criterion is conserving memory.

11. The buffer page system of claim 2, wherein the pixel page controller sets the pixel page geometry to be 16×

32.

12. The buffer page system of claim 2, wherein the pixel page controller sets the pixel page geometry to be 8×

32.

13. The buffer page system of claim 2, wherein the pixel page controller sets the pixel page geometry using a screen resolution of the frame of pixels.

14. The buffer page system of claim 2 further comprising of at least one memory device, each memory device having a plurality of memory pages, wherein the pixel page controller sets the pixel page geometry using a size of the memory pages in each memory device.

15. The buffer page system of claim 14, wherein the pixel page controller sets the pixel page geometry using the number of memory devices available.

16. The buffer page system of claim 14, wherein the pixel page controller sets the pixel page geometry using whether or not burst accessing is available in each memory device.

17. The buffer page system of claim 2, wherein the pixel page controller also sets a pixel page allocation to control how many pixel pages are allocated to one frame of pixels.

18. The buffer page system of claim 2, wherein the pixel page controller adjusts the pixel page geometry as the screen resolution of the frame of pixels changes.

19. A method of controlling pixel page geometry, comprising:

determining one or more criteria for controlling pixel page geometry;

determining a screen resolution of a frame of pixels;

selecting a pixel page geometry based on the one or more criteria and the screen resolution.

20. The method of claim 19, further comprising setting one or more addressing parameters to control addressing according to the selected pixel page geometry.

21. The method of claim 19, further comprising selecting a pixel page allocation to control how many pixel pages are allocated to one frame of pixels.

22. The method of claim 19, where one criterion is reducing page misses.

23. The method of claim 19, wherein one criterion is conserving memory.

24. The method of claim 19, wherein one criterion is maximizing an output data rate.

25. The method of claim 19, further comprising adjusting the pixel page geometry as the screen resolution of the frame of pixels changes.

26. The method of claim 19, further comprising receiving instructions for controlling pixel page geometry.

27. The method of claim 19, wherein determining one or more criteria for controlling pixel page geometry comprises receiving one or more criteria from a video source.

28. A system for controlling pixel page geometry, comprising:

means for determining one or more criteria for controlling pixel page geometry;

means for determining a screen resolution of a frame of pixels; and

means for selecting a pixel page geometry based on the one or more criteria and the screen resolution.

29. The system of claim 28, further comprising means for setting one or more addressing parameters to control addressing according to the selected pixel page geometry.

30. The system of claim 28, further comprising means for selecting a pixel page allocation to control how many pixel pages are allocated to one frame of pixels.

31. The system of claim 28, wherein one criterion is reducing page misses.

32. The system of claim 28, wherein one criterion is conserving memory.

33. The system of claim 28, wherein one criterion is maximizing an output data rate.

34. The system of claim 28, further comprising means for adjusting the pixel page geometry as the screen resolution of the frame of pixels changes.

35. The system of claim 28, further comprising means for receiving instructions for controlling pixel page geometry.

36. The system of claim 28, wherein determining one or more criteria for controlling pixel page geometry comprises receiving one or more criteria from a video source.

37. A system comprising:

a scan converter that receives data elements in a first order and that provides data elements to a data destination in a second order; and

a buffer page controller, for controlling geometry of a plurality of buffer pages wherein the buffer pages corresponds to a plurality of memory pages.

38. The system of claim 37 further comprising a memory controller, for controlling the storage and transmission of the data elements in a memory device.

39. The system of claim 38 further comprising a plurality of ports for connecting to a plurality of memory devices.

40. The system of claim 38 wherein the memory device has a plurality of memory pages including a plurality of memory locations.

41. The system of claim 38 wherein the memory controller generates addresses for storing data elements to and retrieving data elements from the memory device.

42. The system of claim 38 wherein the scan converter stores data elements to one of the plurality of memory pages in the memory device, and wherein each memory page stores data elements in multiple locations corresponding to the first order and retrieves the data elements from multiple locations corresponding to the second order.