Frame rate conversion device, overtaking prediction method for use in the same, display control device and video receiving display device

• US 20050105001A1
• Filed: 09/20/2004
• Published: 05/19/2005
• Est. Priority Date: 09/25/2003
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Matsuzaki, Eiichi, Yui, Hideaki
• Granted Patent: US 7,336,317 B2
• Time in Patent Office: Days
• US Class Current: 348/441
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed

Abstract

An overtaking prediction method of, when input and output of data to and from a common memory are being performed with an input frame frequency and an output frame frequency made different from each other, predicting a frame in which overtaking occurs between the input and the output of the data to and from the memory. The overtaking prediction method includes a step of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of a first parameter corresponding to a difference amount between a progress speed of a write address and a progress speed of a read address and a second parameter corresponding to a difference between a write address and a read address at an overtaking prediction point and to an offset address difference amount between an input offset address and an output offset address.

Claims

1. A frame rate conversion device comprising:

a memory controller which performs input and output of data to and from a common memory while making an input frame frequency and an output frame frequency different from each other;

an overtaking prediction unit which predicts a frame in which overtaking occurs between the input and the output of the data to and from the memory; and

a memory writing controller which brings writing to the memory to a stop when the overtaking prediction unit predicts that the overtaking occurs,

the overtaking prediction unit having a function of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of an offset address difference amount.

3. A frame rate conversion device according to claim 1, wherein the overtaking prediction unit has a function of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of a first parameter calculated by using the input frame frequency, the output frame frequency and one frame of address amount in the input and the output and a second parameter corresponding to a progress speed of a read address at an overtaking prediction point and to an offset address difference amount.

4. A frame rate conversion device according to claim 3, wherein when a progress speed of a write address for the memory is faster than the progress speed of a read address for the memory, a first parameter is derived from a result obtained by dividing by the input frame frequency a difference amount between a result obtained by multiplying one frame of address amount in the input by the input frame frequency and a result obtained by multiplying one frame of address amount in the output by the output frame frequency.

5. A frame rate conversion device according to claim 3, wherein when a progress speed of a write address for the memory is slower than the progress speed of a read address for the memory, a first parameter is derived from a result obtained by dividing by the input frame frequency a difference amount between twice as large as a result obtained by multiplying one frame of address amount in the input by the input frame frequency and a result obtained by multiplying one frame of address amount in the output by the output frame frequency.

6. A frame rate conversion device according to claim 3, wherein a second parameter is derived by performing correction to add the offset address difference amount to a read address during the writing to the memory.

7. A frame rate conversion device according to claim 6, wherein the overtaking prediction unit has a comparison unit which compares a first parameter and a second parameter, the comparison unit having a function of predicting a frame in which overtaking occurs, by effecting switching between comparison conditions according to a difference between a progress speed of a write address for the memory and a progress speed of a read address for the memory.

8. A frame rate conversion device according to claim 7, wherein the overtaking prediction unit has a function of predicting that overtaking occurs, when the progress speed of the write address for the memory is faster than the progress speed of the read address for the memory, while the comparison unit has a function of predicting that overtaking occurs, when the second parameter is smaller than the first parameter.

9. A frame rate conversion device according to claim 7, wherein the overtaking prediction unit has a function of predicting that overtaking occurs, when the progress speed of the write address for the memory is slower than the progress speed of the read address for the memory, while the comparison unit has a function of predicting that overtaking occurs, when the second parameter is larger than the first parameter.

2. A frame rate conversion device comprising:

a memory controller having at least two inputs and operative to perform input and output of data to and from a common memory while making an input frame frequency and an output frame frequency different from each other with respect to each of the inputs;

an overtaking prediction unit provided for each of the inputs to predict a frame in which overtaking occurs between the input and the output of the data to and from the memory; and

a memory writing controller provided for each of the inputs to bring writing to the memory to a stop when the overtaking prediction unit predicts that the overtaking occurs,

the overtaking prediction unit having a function of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of an offset address difference amount.

14. A display control device comprising:

a frame rate conversion device according to claim 2;

and

a multi-picture display position adjustment unit which adjusts a position where the plurality of input data are to be displayed on one screen in the form of synthesized multi-picture display.

10. An overtaking prediction method of, when input and output of data to and from a common memory are being performed with an input frame frequency and an output frame frequency made different from each other, predicting a frame in which overtaking occurs between the input and the output of the data to and from the memory, comprising:

a step of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of an offset address difference amount.

12. A frame rate conversion device comprising:

a memory controller which performs input and output of data to and from a common memory while making an input frame frequency and an output frame frequency different from each other; and

an overtaking prediction unit which predicts a frame in which overtaking occurs between the input and the output of the data to and from the memory,

the overtaking prediction unit being constructed to execute an overtaking prediction method according to claim 10.

13. A display control device comprising:

a frame rate conversion device according to claim 12;

and

a display position control unit which displays the input data on a screen.

15. A video receiving display device comprising:

an image signal generation circuit including a frame rate conversion device according to claim 12;

a video information receiving device which supplies video data to the image signal generation circuit;

a driving circuit to which display data are supplied from the image signal generation circuit; and

an image display device driven by the driving circuit.

16. A video receiving display device according to claim 15, wherein said video information receiving device is capable of selecting a TV channel.

11. An overtaking prediction method of, when input and output of data to and from a common memory are being performed with an input frame frequency and an output frame frequency made different from each other, predicting a frame in which overtaking occurs between the input and the output of the data to and from the memory, comprising:

a step of predicting the frame in which the overtaking occurs between the input and the output of the data, on the basis of a first parameter corresponding to a difference amount between a progress speed of a write address and a progress speed of a read address and a second parameter corresponding to a difference between a write address and a read address at an overtaking prediction point and to an offset address difference amount.