Method and system for wireless digital multimedia transmission

• US 20050105498A1
• Filed: 03/01/2004
• Published: 05/19/2005
• Est. Priority Date: 11/17/2003
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Hardacker, Robert, Desch, David A.
• Granted Patent: US 7,020,121 B2
• Time in Patent Office: Days
• US Class Current: 370/338
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 65/70 Media network packetisation
• CPC Class Codes: H04N 21/2381 Adapting the multiplex stream to a specific network, e.g. an Internet Protocol [IP] network transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04N 21/4363 Adapting the video stream to a specific local network, e.g. a Bluetooth® network
• CPC Class Codes: H04N 21/4381 Recovering the multiplex stream from a specific network, e.g. recovering MPEG packets from ATM cells transmission of MPEG streams over ATM H04L12/5601
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

Digital Visual Interface (DVI), or High Definition Multi-media Interface (HDMI), data is received from a source and sent to a transmitter chip that includes a transition minimized differential signaling (TMDS) receiver that outputs a 3-data and 1-clock physical signaling stream representing the DVI or HDMI data. This stream is rendered into I and Q data by an ASIC or FPGA and sent to a wireless transmitter for modulation, upconverting, and transmission to, e.g., a nearby display device without ever rendering the data into baseband video on the transmitter chip. The display device has a receiver chip that is essentially the inverse of the transmitter chip.

Claims

1. A system, comprising:

a transition minimized differential signaling (TMDS) receiver on a first substrate configured for receiving at least one of;

digital visual interface (DVI) data, and high definition multi-media (HDMI) data;

at least one transmitter processor on the first substrate and receiving data from the TMDS receiver, the transmitter processor being implemented by one of;

a field programmable gate array (FPGA), and application specific integrated circuit (ASIC);

at least one wireless transmitter on the first substrate and receiving data from the transmitter processor for wireless transmission thereof;

at least one wireless receiver configured to receive data from the wireless transmitter;

at least one receiver processor receiving data from the wireless receiver, the receiver processor being implemented by one of;

a field programmable gate array (FPGA), and application specific integrated circuit (ASIC); and

a transition minimized differential signaling (TMDS) transmitter configured for receiving data from the receiver processor and outputting at least one of;

DVI, and HDMI, input signals to a display.

2. The system of claim 1, wherein the system does not reduce data to a baseband video signal during processing.

3. The system of claim 1, wherein at least the transmitter processor includes phase-locked loop circuitry for clock stabilization.

4. The system of claim 1, wherein at least the transmitter processor includes de-jitter circuitry for input data stabilization.

5. The system of claim 1, wherein at least the transmitter processor applies forward error correction prior to differential encoding of data.

6. The system of claim 1, wherein at least the transmitter processor outputs I and Q data to the wireless transmitter.

7. The system of claim 6, wherein the transmitter processor receives three data TMDS data and 1 TMDS clock streams from the TMDS receiver.

8. A method for wireless transmission of video data, comprising:

receiving the video data at a physical signaling stream receiver;

rendering the data into a physical signaling stream;

rendering the physical signaling stream into data suitable for modulation by a radio transmitter, the rendering acts being undertaken without rendering the data into baseband video at any time;

wirelessly transmitting the data;

receiving the data;

rendering demodulated data from the received data;

rendering physical signaling stream data from the demodulated data, the rendering acts being undertaken without rendering the data into baseband video at any time; and

outputting the data to a display device using a physical signaling stream transmitter.

9. The method of claim 8, wherein the physically signaling stream is a 3-data and 1-clock TMDS stream.

10. The method of claim 9, wherein the data suitable for modulation by a radio transmitter that is rendered from the physical signaling stream is I and Q data.

11. A digital video transmitter, comprising:

at least one transmitter processor configured to receive a physical signaling stream representing digital video data and based thereon, without rendering baseband information representing the digital video data, outputting a quadrature signal suitable for processing by a wireless transmitter.

12. The digital video transmitter of claim 11, wherein the processor is an ASIC.

13. The digital video transmitter of claim 11, wherein the processor is an FPGA.

14. The digital video transmitter of claim 11, further comprising the wireless transmitter and a substrate holding the wireless transmitter and the transmitter processor.

15. The digital video transmitter of claim 14, wherein the transmitter processor includes phase-locked loop circuitry for clock stabilization.

16. The digital video transmitter of claim 14, wherein at least the transmitter processor includes de-jitter circuitry for input data stabilization.

17. The digital video transmitter of claim 14, wherein at least the transmitter processor applies forward error correction prior to differential encoding of data.

18. The digital video transmitter of claim 14, wherein at least the quadrature signal is I and Q data and the physical signaling stream is 3-data and 1-clock TMDS information, and the digital video transmitter further comprises a TMDS receiver coupled to the processor.

19. A digital video receiver, comprising:

at least one receiver processor configured to receive a demodulated quadrature signal and based thereon, without rendering baseband information representing the digital video data, outputting a physical signaling stream representing digital video data.

20. The digital video receiver of claim 19, wherein the processor is an ASIC.

21. The digital video receiver of claim 19, wherein the processor is an FPGA.

22. The digital video receiver of claim 19, further comprising a wireless receiver and a substrate holding the wireless receiver and the receiver processor.

23. The digital video receiver of claim 22, wherein at least the quadrature signal is I and Q data and the physical signaling stream is 3-data and 1-clock TMDS information, and the digital video receiver further comprises a TMDS receiver coupled to the processor.