Method and system for the conversion of phase shift keying signals (PSK) into amplitude shift keying signals (ASK)

• US 20050105633A1
• Filed: 09/15/2004
• Published: 05/19/2005
• Est. Priority Date: 03/15/2002
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Samatier I Marti, Josep, Lopez Villegas, Jose Ma.
• Granted Patent: US 6,975,165 B2
• Time in Patent Office: Days
• US Class Current: 375/269
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/227 using coherent demodulation

Abstract

The system consists of a power divider, PDIV, with an input, into which a PSK signal at a frequency of 2f is injected, where f is half the frequency of a carrier signal and with an even number M of outputs, from which corresponding signals, i₁ . . . i_M, are obtained at equal frequency and phase, connected to M argument dividers with tuneable natural resonant frequency, Div₁ . . . Div_M, obtaining M output signals, O₁ . . . O_M, from the said dividers and M−1 power combiners, PC₁ . . . PC_M−1, the inputs of which are connected two by two to the said M output signals, O₁ . . . O_M, providing M−1 ASK signals at the outputs of the said power combiners, which correspond respectively to each of the M−1 possible changes in phase of the said input PSK signal.

Claims

1. A system for phase shift keying (PSK) signal conversion employing digital amplitude shift keying (ASK), characterised because it consists of a power divider, PDIV, with an entrance which is injected with a PSK signal at a frequency of 2f, where f is half the frequency of a carrier signal and with an even number, M, of outputs, from which the corresponding signals i₁ . . . i_M are obtained at equal frequency and phase, respectively connected to M dividers with natural tuneable resonant frequency of Div₁ . . . Div_M, obtaining M output signals O₁ . . . O_M from these same dividers and M−

1 power combiners PC₁ . . . PC<sub>M−

1</sub>, the inputs of which are connected two by two to the said M output signals, providing at the output of these power combiners, M−

1 signals with ASK modulation, which respectively correspond to each of the possible M−

1 phase changes of this PSK input signal.

2. A system in accordance with claim 1, which is characterised because the number of outputs, M, from this power divider, PDIV, is equal to two so that the system performs a conversion of a signal with binary phase shift keying (BPSK) modulation into a digital signal with amplitude shift keying (ASK) modulation, which responds to phase changes of 180°

in the said PSK input signal.

3. A system in accordance with claim 1, which is characterised because the number of outputs M from this power divider PDIV is equal to four so that the system performs a conversion of a signal with quadrature phase shift keying (QPSK) modulation into three signals with digital amplitude shift keying (ASK) modulation, which respectively responds to phase changes of 90°

, −

90° and

180°

in the said PSK input signal.

4. A system in accordance with claim 1, which is characterised because each of the said argument dividers, Div₁, with natural tuneable resonant frequency, is analogue and consists of a T-polarisation circuit, BT, with a first input to which is applied a constant dc voltage, a second input to which the said signal i_i is applied and a tuneable resonance circuit connected to the output.

5. A system in accordance with claim 4, which is characterised because this same tuneable resonance circuit consists of an inverter transformer T1, two varactor (variable capacitance) diodes, V1 and V2, connected to the ends of each winding of the said inverter transformer, arranged in-line, connected in opposition, enabling a mid point for controlling the capacitance by means of a voltage Vc which is used to dynamically tune the natural resonant frequency, together with a power stage consisting of a circuit with a global response which provides a negative differential impedance, so that this power stage compensates the losses and increases the argument divider sensitivity, taking the output signal from the said varactor diode terminals.

6. A system in accordance with claim 4, which is characterised because this same tuneable resonance circuit consists of an inverter transformer, two varactor (variable capacitance) diodes connected to the ends of each winding of the said inverter transformer, arranged in-line, connected in opposition, enabling a mid point for controlling the capacitance by means of a voltage Vc which is used to dynamically tune the natural resonant frequency and a transformer which produces the output signal.

7. A system in accordance with claim 4, which is characterised because each of the said dividers, Div_i, has a tuneable natural resonant frequency that is fixed during manufacture by the specifications of its components.

8. A system in accordance with claim 5, which is characterised because the said global response circuit which provides a negative differential impedance consists of a current source S1 and cross-coupled transistors Q1 and Q2.

9. A system in accordance with claim 8, which is characterised because the said transistors are MOSFET type, and this cross-coupling is achieved by connecting Q1 drain to Q2 gate and vice-versa and the sources of the transistors are connected to current source S1.

10. A system in accordance with claim 8, which is characterised because the said transistors are BIPOLAR type, and this cross-coupling is achieved by connecting Q1 collector to Q2 base and vice-versa and the emitters of the transistors are connected to current source S1.

11. A system in accordance with claim 4, which is characterised because said argument dividers, Div₁ . . . Div_M, are identical, producing architectural symmetry and determining that the output signals, O₁ . . . O_M, are equal in both power and frequency.

12. A method for converting digital PSK signals into digital ASK signals for a system consisting of power divider PDIV with an even number of outputs M, M argument dividers with tuneable natural resonance frequency, Div₁ . . . Div_M, and M−

1 power combiners, PC₁ . . . PC<sub>M−

1</sub>, which provide outputs of M−

1 ASK signals, characterised because it consists of the following steps;

(a) Tuning by means of voltage Vc with each divider Div₁ . . . Div_M corresponding to a respective resonant frequency value f₁ . . . f_M from among an increasing set of M values, so that the first half of these frequencies is less than f and a second half of the same frequencies is greater than f;

(b) Injecting a PSK input signal at a frequency of 2f into the said power divider PDIV;

(c) Obtaining identical i₁ . . . i_M signals at the M outputs from the said power divider PDIV;

(d) Injecting the said signals i₁ . . . i_M into the respective inputs of dividers, Div₁ . . . Div_M and obtaining corresponding output signals, O₁ . . . O_M,after a process of phase and frequency locking of the natural resonant frequency of each one of its initial value fi to value f, together with phase locking at an equilibrium value between the two possible values;

(e) injecting the said output signals, O₁ . . . O_M, taken two by two, at each of the respective M−

1 power combiners, PC₁ . . . PC<sub>M−

1</sub>, where they mix either additively or subtractively so that M−

1 ASK modulation signals are produced, which respectively respond to each of the possible M−

1 changes in phase of the said PSK input signal.