Single poly CMOS imager

• US 20050106773A1
• Filed: 12/28/2004
• Published: 05/19/2005
• Est. Priority Date: 10/21/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Rhodes, Howard E.
• Granted Patent: US 7,557,024 B2
• Time in Patent Office: Days
• US Class Current: 438/48
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

More complete charge transfer is achieved in a CMOS or CCD imager by reducing the spacing in the gaps between gates in each pixel cell, and/or by providing a lightly doped region between adjacent gates in each pixel cell, and particularly at least between the charge collecting gate and the downstream to the charge collecting gate. To reduce the gaps between gates, an insulator cap with spacers on its sidewalls is formed for each gate over a conductive layer. The gates are then etched from the conductive layer using the insulator caps and spacers as hard masks, enabling the gates to be formed significantly closer together than previously possible, which, in turn increases charge transfer efficiency. By providing a lightly doped region on between adjacent gates, a more complete charge transfer is effected from the charge collecting gate.

Claims

1. A process for fabricating a semiconductor device comprising:

providing a substrate;

forming a conductive layer over the substrate;

forming a plurality of gate-like structures protruding from the conductive layer, each gate-like structure having a first gate width and sidewalls and is separated from each adjacent gate-like structure by a first gap width;

forming spacers on the sidewalls of the gate-like structures to thereby reduce said first gap width between adjacent gate-like structures; and

etching the conductive layer using the gate-like structures and spacers as masks to form a plurality of conductive gate structures each having a second gate width approximately corresponding to the first gate width plus the width of two of said spacers, wherein adjacent ones of said conductive gate structures are separated from each other by a second gap width approximately corresponding to the first gap width minus the width of two of said spacers.

2. The process according to claim 1, wherein forming the plurality of gate-like structures comprises:

forming an insulating layer over the conductive layer, and

patterning the insulating layer to form a plurality of insulator caps, wherein the plurality of insulator caps are the plurality of gate-like structures,

wherein the conductive layer is etched using the insulator caps and spacers as hard masks to form the plurality of conductive gate structures.

3. The process according to claim 1, wherein forming the gate-like structures comprises

depositing a resist layer on the conductive layer,

patterning the resist layer according to a desired arrangement of gates to be formed from the conductive layer, and

partially etching through the conductive layer to form the gate-like structures,

and wherein etching the conductive layer to form the conductive gates results in removal of the remainder of the conductive layer except for the regions defined by the gate-like structures and the regions on the partially etched conductive layer covered by the spacers.

4. The process according to claim 3, wherein

the partial etching of the conductive layer with the patterned resist thereon results in the gate-like structures being formed as a plurality of substantially unetched regions of the conductive layer,

the partial etching of the conductive layer reduces the thickness of the conductive layer to approximately one-half of the original thickness thereof, except at the substantially unetched regions defining the gate-like structures, and

etching the conductive layer to form the conductive gates results in removal of the remainder of the conductive layer except for the regions defined by the gate-like structures and the regions on the partially etched conductive layer covered by the spacers.

5. The process according to claim 1, further comprising:

lightly doping a region between two adjacent ones of the plurality of conductive gate structures.

6. The process according to claim 5, wherein lightly doping the region between two adjacent conductive gate structures is performed by implanting into the region a concentration of ions in the range of about 3·

10¹¹ ions/cm² to about 1·

10¹⁴ ions/cm².

7. The process according to claim 6, wherein lightly doping the region between two adjacent conductive gate structures is performed by implanting into the region a concentration of ions in the range of about 1·

10¹² ions/cm² to about 1·

10¹³ ions/cm².

8. A process for fabricating a semiconductor device comprising:

providing a substrate;

forming a conductive layer over the substrate;

patterning the conductive layer to form a plurality of gate structures; and

lightly doping a region between two adjacent ones of the plurality of gate structures.

9. The process according to claim 8, wherein lightly doping the region between two adjacent gate structures is performed by implanting into the region a concentration of ions in the range of about 3·

10¹¹ ions/cm² to about 1·

10¹⁴ ions/cm².

10. The process according to claim 9, wherein lightly doping the region between two adjacent gate structures is performed by implanting into the region ions in the range of about 1·

10¹² ions/cm² to about 1·

10¹³ ions/cm².

11-44. -44. (canceled)