System and method for testing a memory with an expansion card using DMA

• US 20050107987A1
• Filed: 11/14/2003
• Published: 05/19/2005
• Est. Priority Date: 11/14/2003
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Pomaranski, Ken G., Shidla, Dale J., Barr, Andrew H.
• Granted Patent: US 7,797,134 B2
• Time in Patent Office: Days
• US Class Current: 702/186
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test

Abstract

A computer system that includes a processor, a memory controller coupled to the processor, a memory coupled to the memory controller, a first input/output (I/O) controller coupled to the memory controller, a first expansion slot coupled to the first I/O controller, and a test module card coupled to the first expansion slot wherein the test module card is configured to cause tests to be performed on the memory using direct memory access (DMA) is provided.

Claims

1. A computer system comprising:

a processor;

a memory controller coupled to the processor;

a memory coupled to the memory controller;

a first input/output (I/O) controller coupled to the memory controller;

a first expansion slot coupled to the first I/O controller; and

a test module card coupled to the first expansion slot;

wherein the test module is configured to cause tests to be performed on the memory using direct memory access (DMA).

2. The computer system of claim 1 further comprising:

an operating system;

wherein the processor is configured to cause the operating system to be booted, and wherein the test module card is configured to cause the tests to be performed on the memory using the first bus subsequent to the operating system being booted.

3. The computer system of claim 1 further comprising:

an operating system;

wherein the processor is configured to cause the operating system to be executed, and wherein the test module card is configured to cause the tests to be performed on the memory using the first bus during execution of the operating system.

4. The computer system of claim 1 further comprising:

a second I/O controller coupled to the memory controller;

a second expansion slot coupled to the second I/O controller; and

an I/O device coupled to the second expansion slot.

5. The computer system of claim 1 wherein the test module card is configured to cause tests to be performed on the memory by providing read and write transactions to the first I/O controller.

6. The computer system of claim 5 wherein the read and write transactions comprise DMA transactions.

7. The computer system of claim 1 further comprising:

a bus bridge coupled to the processor and the first I/O controller.

8. The computer system of claim 1 further comprising:

a system controller that comprises the memory controller.

9. A method performed by a test module card coupled to an input/output (I/O) controller in a computer system that includes a memory comprising:

selecting a portion of the memory for testing during operation of the computer system;

generating a test transaction; and

providing the test transaction to the portion using direct memory access (DMA).

10. The method of claim 9 further comprising:

detecting an error that occurs in response to the test transaction; and

performing a remedial action in response to detecting the error.

11. The method of claim 9 further comprising:

providing the test transaction from the test module to the I/O controller;

providing the test transaction from the I/O controller to a bus bridge;

providing the test transaction from the bus bridge to a system bus;

providing the test transaction from the system bus to a memory controller; and

providing the test transaction from the memory controller to the portion.

12. The method of claim 11 further comprising:

storing information in the memory in response to the test transaction being a write transaction.

13. The method of claim 11 further comprising:

in response to the test transaction being a read transaction;

providing information associated with the test transaction from the portion to the memory controller;

providing the information from the memory controller to the system bus;

providing the information from the system bus to the bus bridge;

providing the information from the bus bridge to the I/O controller; and

providing the information from the I/O controller to the test module.

14. The method of claim 9 further comprising:

providing the test transaction from the test module to the I/O controller;

providing the test transaction from the I/O controller to a system controller;

providing the test transaction from the system controller to a memory controller; and

providing the test transaction from the memory controller to the portion.

15. A computer system comprising:

a processor;

a memory controller coupled to the processor and configured to perform error correction;

a memory coupled to the memory controller;

an input/output (I/O) controller coupled to the memory controller;

an expansion slot coupled to the I/O controller; and

a test module card coupled to the expansion slot;

wherein the test module is configured to cause tests to be performed on the memory by providing read transactions associated with the memory to the I/O controller.

16. The computer system of claim 15 further comprising:

an operating system;

wherein the processor is configured to cause the operating system to be booted, and wherein the test module is configured to cause the tests to be performed on the memory using DMA subsequent to the operating system being booted.

17. The computer system of claim 15 further comprising:

an operating system;

wherein the processor is configured to cause the operating system to be executed, and wherein the test module is configured to cause the tests to be performed on the memory using DMA during execution of the operating system.

18. The computer system of claim 15 wherein the bus comprises a system bus.

19. The computer system of claim 15 wherein the test module is configured to cause tests to be performed on the memory using direct memory access (DMA).

20. The computer system of claim 15 wherein the read transactions comprise direct memory access (DMA) transactions.