Bitstream buffer manipulation with a SIMD merge instruction

• US 20050108312A1
• Filed: 07/01/2003
• Published: 05/19/2005
• Est. Priority Date: 10/29/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chen, Yen-Kuang, Holliman, Matthew, Debes, Eric L., Young, Minerva M., Macy, William W. Jr.
• Granted Patent: US 7,818,356 B2
• Time in Patent Office: Days
• US Class Current: 708/513
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 17/147 Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform G06F17/145 takes precedence
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Claims

1. A method comprising:

determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block; and

performing a shift merge operation to merge said unprocessed data bits from said first data block with a second data block, wherein a merged data block is formed.

2. The method of claim 1 further comprising receiving said first data block and said second data block from a bitstream.

3. The method of claim 1 wherein said first data block and said second data block are loaded from bitstream data in memory.

4. The method of claim 2 further comprising extracting a merged variable length symbol from said merged data block, said merged variable length symbol comprised of said unprocessed data bits and a plurality of data bits from said second data block.

5. The method of claim 4 wherein said merged variable length symbol is sent to a register.

6. The method of claim 4 further comprising:

evaluating said merged data block for variable length symbols;

extracting any whole variable length symbols located in said second data block; and

sending an extracted whole variable length symbols to a register.

7. The method of claim 6 wherein each of said variable length symbols is comprised of at least N-bits of data.

8. The method of claim 7 wherein N is a number greater than one.

9. The method of claim 2 wherein said first data block is held in a first single instruction multiple data register.

10. The method of claim 3 wherein said first single instruction multiple data register is a buffer.

11. The method of claim 2 wherein said second data block is held in a second single instruction multiple data register.

12. The method of claim 1 wherein said shift merge operation is a single instruction multiple data type of instruction to cause a parallel shift right merge of data operands based on a shift count.

13. The method of claim 10 wherein said shift merge operation operates on data elements at a byte granularity.

14. The method of clam 10 wherein said shift merge operation operates on data elements at a bit granularity.

15. An apparatus comprising:

an execution unit to execute a plurality of instructions for a variable length decoding algorithm, wherein one of said instructions is a first instruction for a shift merge operation, said plurality of instructions to cause said execution unit to;

determine whether any unprocessed data bits for a partial variable length symbol exist in a first data block; and

perform a shift merge operation to merge said unprocessed data bits from said first data block with a second data block, wherein a merged data block is formed.

16. The apparatus of claim 15 wherein plurality of instructions further cause said execution unit to extract a merged variable length symbol from said merged data block, said merged variable length symbol comprised of said unprocessed data bits and a plurality of data bits from said second data block.

17. The apparatus of claim 15 wherein said first data block and said second data block are received from a bitstream.

18. The apparatus of claim 16 wherein said plurality of instructions further cause said execution unit to:

evaluate said merged data block for variable length symbols; and

extract any whole variable length symbols located in said second data block.

19. The apparatus of claim 18 wherein each of said variable length symbols is comprised of at least two bits of data.

20. The apparatus of claim 19 wherein said first data block and said second data block are held in a first single instruction multiple data register and a second single instruction multiple data register, respectively.

21. The apparatus of claim 20 wherein said first single instruction multiple data register is a buffer.

22. The apparatus of claim 21 wherein said shift merge operation is a single instruction multiple data type of instruction to cause a parallel shift right merge of data operands based on a shift count.

23. The apparatus of claim 22 wherein said shift merge operation is to operate on data elements at a byte granularity.

24. An article comprising a machine readable medium that stores a program, said program being executable by a machine to perform a method comprising:

determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block; and

performing a shift merge operation to merge said unprocessed data bits from said first data block with a second data block, wherein a merged data block is formed.

25. The article of claim 24 wherein said first data block and said second data block are to be loaded from a data bitstream.

26. The article of claim 25 wherein said method further comprises extracting a merged variable length symbol from said merged data block, said merged variable length symbol comprised of said unprocessed data bits and a plurality of data bits from said second data block.

27. The article of claim 26 wherein each of said variable length symbols is comprised of at least two bits of data.

28. The article of claim 24 wherein said shift merge operation is a single instruction multiple data type of instruction to cause a parallel shift right merge of data operands based on a shift count.

29. The article of claim 26 wherein said method further comprises:

evaluating said merged data block for variable length symbols; and

extracting any whole variable length symbols located in said second data block.

30. A system comprising:

a memory to store data and instructions,

a processor coupled to said memory on a bus, said processor operable to perform instructions for a variable length decoding algorithm, said processor comprising;

a bus unit to receive a sequence of instructions from said memory;

an execution unit coupled to said bus unit, said execution unit to execute said sequence, said sequence to include a first instruction for a shift merge operation, said sequence to cause said execution unit to;

determine whether any unprocessed data bits for a partial variable length symbol exist in a first data block; and

perform a shift merge operation to merge said unprocessed data bits from said first data block with a second data block, wherein a merged data block is formed.

31. The system of claim 30 wherein said first data block and said second data block are loaded from bitstream data.

32. The system of claim 30 wherein said plurality of instructions further cause said execution unit to extract a merged variable length symbol from said merged data block, said merged variable length symbol comprised of said unprocessed data bits and a plurality of data bits from said second data block.

33. The system of claim 32 wherein said plurality of instructions further cause said execution unit to:

evaluate said merged data block for variable length symbols; and

extract any whole variable length symbols located in said second data block.

34. The system of claim 33 wherein each of said variable length symbols is comprised of at least two bits of data.

35. The system of claim 34 wherein said first data block and said second data block are held in a first single instruction multiple data register and a second single instruction multiple data register, respectively.

36. The system of claim 35 wherein said shift merge operation is a single instruction multiple data type of instruction to cause a parallel shift right merge of data operands based on a shift count.

37. The system of claim 36 wherein at least a single edge for at least one or more of said variable length symbols is not aligned at a byte boundary.

38. The system of claim 37 wherein said shift merge operation is to operate on data elements at a bit granularity.

39. The system of claim 37 wherein said shift merge operation is to operate on data elements at a byte granularity.