MEMORY DEVICE WITH PROGRAMMABLE RECEIVERS TO IMPROVE PERFORMANCE

• US 20050108468A1
• Filed: 11/18/2003
• Published: 05/19/2005
• Est. Priority Date: 11/18/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Hazelzet, Bruce G., Kellogg, Mark W., Rankin, Darcie J.
• Granted Patent: US 7,646,649 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A memory system having a plurality of DRAMs which are selectively provided non-inverted or inverted signals. The DRAMs have the ability to accept non-inverted or inverted address/command signals from a register that drives a plurality of signals simultaneously. The system includes DRAM receivers with programmable input polarity and a register with programmable output polarity.

Claims

1. A memory system comprising:

a plurality of DRAMs having circuits to accept non-inverted input signals and inverted input signals.

a register programmed to provide inverted or non-inverted signals to the DRAMS.

2. The memory system of claim 1 which includes re-drive circuitry, which can output both non-inverted and inverted polarity signals from one or more input signals.

3. A memory system according to claim 1 which includes:

Programmable pins in the register and DRAMs to operate in either non-inverted or inverted mode.

4. A memory system according to claim 3 wherein the DRAMs are mounted on a DIMM.

5. The memory system of claim 3 wherein one programmable pin is connected to ground to provide one mode and the other programmable pin is connected to Vdd to operate in the other mode.

9. A memory system of claim 1 in which the register drives either non-inverted or inverted signals to the DRAMs using a programmable pin.

6. A memory system comprising:

a plurality of DRAMs having circuits to accept non-inverted input signals and inverted input signals; and

a memory controller which can drive either non-inverted or inverted signals to the DRAMs using a programmable pin.

7. A memory system according to claim 6 wherein the memory controller may operate in one mode at powerup and a means for changing modes after powerup.

8. The memory system of claim 6 wherein the pin is hard-wired to the DRAMs.

10. A memory system comprising:

a module having a plurality of DRAMs with inputs and outputs and circuits to accept either non-inverted input signals and inverted input signals;

a means connected to the circuits for changing modes to accept inverted input signals; and

a memory controller which is programmable to operate in non-inverted mode at power up and to change after it is programmed.

11. A memory system of claim 10 wherein pre-selected DRAMs may operate in the inverted mode with some critical signals remaining in a non-inverted mode.

12. The memory system of claim 10 wherein the memory controller may operate in the inverted mode with some critical signals remaining in non-inverted mode.

13. The memory system of claim 10 wherein a programmable pin is hard-wired to the module.

14. The memory system of claim 10 wherein the means for changing modes includes a pin that is controlled by the memory controller.

15. A DIMM comprising:

a plurality of DRAMs with means for operating with non-inverted or inverted signals based on a pre-selected operating mode; and

signal re-drive circuitry which generates an output in both non-inverted and inverted polarity signals from one or more input signals.

16. A computer system with a memory system comprising:

memory devices and re-drive circuitry external to the said memory devices, said re-drive circuitry having means for outputting both non-inverted and inverted polarity signals from one or more input signals, and said memory devices designed to operate with non-inverted or inverted signals based on a selected operating mode.