Security of program executables and microprocessors based on compiler-arcitecture interaction

• US 20050108507A1
• Filed: 11/12/2004
• Published: 05/19/2005
• Est. Priority Date: 11/17/2003
• Status: Active Grant

• Current Assignee: BlueRISC Inc.
• Original Assignee: BlueRISC Inc.
• Inventors: Carver, Kristopher, Ashok, Raksit, Chheda, Saurabh
• Granted Patent: US 7,996,671 B2
• Time in Patent Office: Days
• US Class Current: 712/209
• CPC Class Codes: G06F 21/125 by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30156 Special purpose encoding of instructions, e.g. Gray coding
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification

Abstract

A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction.

Claims

1. A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings.

2. The method of claim 1 wherein:

a control instruction encoded with an instruction set encoding contains information about decoding of a second instruction;

the second instruction is encoded with a different instruction set encoding from the control instruction.

3. The method of claim 2, wherein instruction set encodings are randomly generated at compile time.

4. The method of claim 2, further comprising of:

adding at compile time to an executable information enabling decoding of an instruction;

the information is added in an encrypted format.

5. The method of claim 2, wherein a constant field within an instruction is scrambled at compile time.

6. The method of claim 2, wherein instructions are scrambled with additional random keys associated with logical program addresses.

10. The method of claim 2, wherein control instructions are implemented as co-processor instructions.

11. The method of claim 1, comprising of:

analyzing a program executable at compile time;

changing the instruction set architecture encoding of an instruction;

scrambling constant fields in an instruction;

adding information about the instruction set encoding of an instruction into another instruction;

generating a program executable with plural instruction set encodings;

7. A processor framework wherein:

instructions are encoded in plural instruction set architectures;

an instruction is decoded during execution with the help of information provided by a previously decoded instruction.

8. The processor framework of method 2, wherein a control instruction is extracted at runtime before entering the processor pipeline.

9. The method of processor framework 7 wherein instructions are decoded to a reference instruction set before entering the decode stage of the processor.

12. A method, for use in a processor context, wherein:

instructions in a program executable are scrambled;

a control instruction scrambled with a key contains information about decoding of an instruction that is scrambled with another key.