Method of fabricating a semiconductor device

• US 20050110016A1
• Filed: 12/17/2004
• Published: 05/26/2005
• Est. Priority Date: 11/17/1998
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 7,172,928 B2
• Time in Patent Office: Days
• US Class Current: 257/66
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66492 with a pocket or a lightly doped drain selectively formed at the side of the gate
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 50/8445 multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
• CPC Class Codes: H10K 59/10 OLED displays
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n⁻-type impurity regions are formed between a channel formation region and n⁺-type impurity regions. Some of the n⁻-type impurity regions overlap with a gate electrode, and the other n⁻-type impurity regions do not overlap with the gate electrode. Since the two kinds of n⁻-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Claims

1. A method of fabricating an active matrix display device, said method comprising the steps of:

forming an insulating film being in contact with a semiconductor layer;

forming a gate electrode intersecting with the semiconductor layer through the insulating film;

first adding an impurity with one conductivity into the semiconductor layer through at least a portion of the gate electrode; and

second adding the impurity into the semiconductor layer without passing through the gate electrode;

wherein an angle between a side of the gate electrode and the insulating film is in a range of 3°

to 60°

.

2. The method of fabricating an active matrix display device according to claim 1, wherein the impurity is added into the semiconductor layer using a mask covering the gate electrode and having a width wider than the gate electrode in a channel length direction in the second adding step.

3. The method of fabricating an active matrix display device according to claim 1, wherein said active matrix display device is an active matrix liquid crystal device.

4. A method of fabricating an active matrix display device, said method comprising the steps of:

forming an insulating film being in contact with a semiconductor layer;

forming a first conductive film being in contact with the insulating film;

forming a second conductive film being in contact with the first conductive film;

forming a gate electrode by patterning the first conductive film and the second conductive film;

wherein the gate electrode includes a first gate electrode and a second gate electrode being formed on the first gate electrode;

wherein the second gate electrode has a width narrower in a channel length direction than the first gate electrode;

first adding an impurity with one conductivity into the semiconductor layer through a portion of the first gate electrode; and

second adding the impurity into the semiconductor layer without passing through the gate electrode;

wherein an angle between a side of the first gate electrode and the insulating film is in a range of 3°

to 60°

.

5. The method of fabricating an active matrix display device according to claim 4, wherein the impurity is added into the semiconductor layer using a mask covering the first gate electrode and having a width wider than the first gate electrode in a channel length direction.

6. The method of fabricating an active matrix display device according to claim 4, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

7. The method of fabricating an active matrix display device according to claim 4, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

8. The method of fabricating an active matrix display device according to claim 4, wherein said first gate electrode comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

9. The method of fabricating an active matrix display device according to claim 4, wherein said second gate electrode comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.

10. The method of fabricating an active matrix display device according to claim 4, wherein said angle is in a range of 5°

to 45°

.

11. A method of fabricating a semiconductor device including a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising the steps of:

forming a first semiconductor layer and a second semiconductor layer;

forming an insulating film being in contact with the first semiconductor layer and the second semiconductor layer;

forming a first gate wiring intersecting with the first semiconductor layer the second semiconductor layer,

forming a second gate wiring on the first gate wiring;

first adding an n-type impurity into the first semiconductor layer through a portion of the first gate wiring;

second adding the n-type impurity into the first semiconductor layer without passing through the first gate wiring; and

third adding a p-type impurity into the second semiconductor layer using the first gate wiring and the second gate wiring as masks,

wherein an angle between a side portion of the first gate wiring intersecting with the first semiconductor layer and the insulating film is in a range of 3°

to 60°

.

12. The method of fabricating an active matrix display device according to claim 11, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

13. The method of fabricating an active matrix display device according to claim 11, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

14. The method of fabricating an active matrix display device according to claim 11, wherein said first gate wiring comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

15. The method of fabricating an active matrix display device according to claim 11, wherein said second gate wiring comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.

16. The method of fabricating an active matrix display device according to claim 11, wherein said angle is in a range of 5°

to 45°

.

17. A method of fabricating a semiconductor device including a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising the steps of:

forming a first semiconductor layer and a second semiconductor layer;

forming an insulating film being in contact with the first semiconductor layer and the second semiconductor layer;

forming a first gate wiring intersecting with the first semiconductor layer and the second semiconductor layer;

forming a second gate wiring on the first gate wiring;

first adding a p-type impurity into the second semiconductor layer using the first gate wiring and the second gate wiring as masks;

second adding an n-type impurity into the first semiconductor layer through a portion of the first gate wiring; and

third adding the n-type impurity into the first semiconductor layer without passing through the first gate wiring;

wherein an angle between a side portion of the first gate wiring intersecting with the first semiconductor layer and the insulating film is in a range of 3°

to 60°

.

18. The method of fabricating an active matrix display device according to claim 17, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

19. The method of fabricating an active matrix display device according to claim 17, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

20. The method of fabricating an active matrix display device according to claim 17, wherein said first gate wiring comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

21. The method of fabricating an active matrix display device according to claim 17, wherein said second gate wiring comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.

22. The method of fabricating an active matrix display device according to claim 17, wherein said angle is in a range of 5°

to 45°

.

23. A method of fabricating a semiconductor device including a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising the steps of:

forming a first semiconductor layer and a second semiconductor layer;

forming an insulating film being in contact with the first semiconductor layer and the second semiconductor layer;

forming a first gate wiring intersecting with the first semiconductor layer and the second semiconductor layer;

forming a second gate wiring on the first gate wiring;

first adding a p-type impurity into the second semiconductor layer using the first gate wiring and the second gate wiring as masks;

second adding an n-type impurity into the first semiconductor layer without passing through the first gate wiring; and

third adding the n-type impurity into the first semiconductor layer through at least a portion of the first gate wiring;

wherein an angle between a side of a portion intersecting with the first semiconductor layer and the insulating film is in a range of 3°

to 60°

.

24. The method of fabricating an active matrix display device according to claim 23, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

25. The method of fabricating an active matrix display device according to claim 23, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

26. The method of fabricating an active matrix display device according to claim 23, wherein said first gate wiring comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

27. The method of fabricating an active matrix display device according to claim 23, wherein said second gate wiring comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.

28. The method of fabricating an active matrix display device according to claim 23, wherein said angle is in a range of 5°

to 45°

.

29. A method of fabricating a semiconductor device including a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising the steps of:

forming a first semiconductor layer and a second semiconductor layer;

forming an insulating film being in contact with the first semiconductor layer and the second semiconductor layer;

forming a first gate wiring intersecting with the first semiconductor layer and the second semiconductor layer;

forming a second gate wiring on the first gate wiring;

first adding an n-type impurity into the first semiconductor layer through a portion of the first gate wiring;

second adding a p-type impurity into the second semiconductor layer using the first gate wiring and the second gate wiring as masks; and

third adding the n-type impurity into the first semiconductor layer without passing through the first gate wiring;

wherein an angle between a side portion of the first gate wiring intersecting with the first semiconductor layer and the insulating film is in a range of 3°

to 60°

.

30. The method of fabricating an active matrix display device according to claim 29, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

31. The method of fabricating an active matrix display device according to claim 29, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

32. The method of fabricating an active matrix display device according to claim 29, wherein said first gate wiring comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

33. The method of fabricating an active matrix display device according to claim 29, wherein said second gate wiring comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.

34. The method of fabricating an active matrix display device according to claim 29, wherein said angle is in a range of 5°

to 45°

.

35. A method of fabricating a semiconductor device including a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising the steps of:

forming a first semiconductor layer and a second semiconductor layer;

forming an insulating film being in contact with the first semiconductor layer and the second semiconductor layer;

forming a first gate wiring intersecting with the first semiconductor layer and the second semiconductor layer;

forming a second gate wiring on the first gate wiring;

first adding an n-type impurity into the first semiconductor layer without passing through the first gate wiring;

second adding a p-type impurity into the second semiconductor layer using the first gate wiring and the second gate wiring as masks; and

third adding the n-type impurity into the first semiconductor layer through a portion of the first gate wiring;

wherein an angle between a side portion of the first gate wiring intersecting with the first semiconductor layer and the insulating film is in a range of 3°

to 60°

.

36. The method of fabricating an active matrix display device according to claim 35, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

37. The method of fabricating an active matrix display device according to claim 35, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

38. The method of fabricating an active matrix display device according to claim 35, wherein said first gate wiring comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

39. The method of fabricating an active matrix display device according to claim 35, wherein said second gate wiring comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.

40. The method of fabricating an active matrix display device according to claim 35, wherein said angle is in a range of 5°

to 45°

.

41. A method of fabricating a semiconductor device including a CMOS circuit having an n-channel thin film transistor and a p-channel thin film transistor, said method comprising the steps of:

forming a first semiconductor layer and a second semiconductor layer;

forming an insulating film being in contact with the first semiconductor layer and the second semiconductor layer;

forming a first gate wiring intersecting with the first semiconductor layer and the second semiconductor layer;

forming a second gate wiring on the first gate wiring;

first adding an n-type impurity into the first semiconductor layer without passing through the first gate wiring;

second adding the n-type impurity into the first semiconductor layer through a portion of the first gate wiring; and

third adding a p-type impurity into the second semiconductor layer using the first gate wiring and the second gate wiring as masks;

wherein an angle between a side portion of the first gate wiring intersecting with the first semiconductor layer and the insulating film is in a range of 3°

to 60°

.

42. The method of fabricating an active matrix display device according to claim 41, wherein said insulating film is a single layer of silicon oxide, silicon nitride or silicon nitride oxide.

43. The method of fabricating an active matrix display device according to claim 41, wherein said insulating film is a multi-layer including a silicon nitride oxide film and a silicon oxide film.

44. The method of fabricating an active matrix display device according to claim 41, wherein said first gate wiring comprises a metal selected from the group consisting of chromium, tantalum, titanium, tungsten and molybdenum.

45. The method of fabricating an active matrix display device according to claim 41, wherein said second gate wiring comprises a metal selected from the group consisting of aluminum, copper, chromium, tantalum, titanium, tungsten and molybdenum.