High light efficiency of GaN-series of light emitting diode and its manufacturing method thereof

• US 20050110031A1
• Filed: 09/27/2004
• Published: 05/26/2005
• Est. Priority Date: 11/25/2003
• Status: Abandoned Application

• Current Assignee: Supernova Optoelectronics Corp.
• Original Assignee: Supernova Optoelectronics Corp.
• Inventors: Hon, Schang-Jing, Lai, Mu-Jen
• Application Number:
  US10/950,132
• Publication Number:
  US 20050110031A1
• Time in Patent Office: Days
• US Class Current: 257/97
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A high light efficiency of GaN-series of light emitting diode and its manufacturing method thereof disclose a process and structure of a p-type semiconductor layer of surface texture structure generation. The optical waveguide effect can be interrupted and the possibility of hexagonal shaped pits defect generated can be reduced through said texture structure. The method explores that controlling the tension and compression of strain while a p-type cladding layer and a p-type transition layer are generated, and then a p-type ohmic contact is formed on said p-type transition layer. Through the control and its structure of said epitaxial growth process, the surface of said p-type semiconductor layer is with texture structure to increase external quantum efficiency and its operation life.

Claims

1. A high light efficiency of GaN-series of light emitting diode comprising:

a substrate;

a semiconductor, which formed on the said substrate that including a n-type semiconductor, a light emitting layer, a p-type semiconductor layer;

wherein said light emitting layer is between said n-type semiconductor layer and said p-type semiconductor layer, and the surface of said p-type semiconductor layer have a texture that generated from a epitaxial process.

2. The light emitting diode in accordance with claim 1, wherein the surface of said p-type semiconductor layer having a texture can interrupt optical waveguide effect.

3. The high light efficiency of GaN-series of light emitting diode in accordance with claim 1, wherein the surface of said p-type semiconductor layer having a texture is formed by controlling the strain during epitaxy of p-type semiconductor layer.

4. The light emitting diode in accordance with claim 1, wherein the said p-type semiconductor layer further comprising a p-type cladding layer and a p-type transition layer formed on said p-type cladding layer and a p-type ohmic contact layer formed on said p-type transition layer.

5. The light emitting diode in accordance with claim 1, wherein further comprising a reflection layer under said light emitting layer.

6. The light emitting diode in accordance with claim 1, wherein said substrate is selected from one of sapphire, silicon carbide, zinc oxide, zirconium diboride, gallium arsenide or silicon.

7. The light emitting diode in accordance with claim 1, wherein said n-type semiconductor layer can be presented as N—

B_xAl_yIn_zGa_1-x-y-zN_pAs_q (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, 0≦

p≦

1, 0≦

q≦

1, and x+y+z=1, p+q=1), or presented as N—

B_xAl_yIn_zGa_1-x-y-zN_pP_q (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, 0≦

p≦

1, 0≦

q≦

1, and x+y+z=1, p+q=1).

8. The light emitting diode in accordance with claim 1, wherein said p-type semiconductor layer can be presented as P—

B_xAl_yIn_zGa_1-x-y-zN_pAs_q (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, 0≦

p≦

1, 0≦

q≦

1, and x+y+z=1, p+q=1), or presented as P—

B_xAl_yIn_zGa_1-x-y-zN_pP_q (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, 0≦

p≦

1, 0≦

q≦

1, and x+y+z=1, p+q=1).

9. The light emitting diode in accordance with claim 1, wherein said light emitting can be composed by one of B_xAl_yIn_zGa_1-x-y-zN_pAs_q (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, 0≦

p≦

1, 0≦

q≦

1, and x+y+z=1, p+q=1), or presented as B_xAl_yIn_zGa_1-x-y-zN_pP_q (0≦

x≦

1, 0≦

y≦

1, 0≦

z≦

1, 0≦

p≦

1, 0≦

q≦

1, and x+y+z=1, p+q=1), or combined by the two aforementioned layer to form quantum well structure.

10. The light emitting diode in accordance with claim 4, wherein said p-type cladding layer is a cladding layer which alters tension strain.

11. The light emitting diode in accordance with claim 4, wherein said p-type transition layer is superlattice structure composed by a semiconductor layer.

12. The light emitting diode in accordance with claim 4, wherein said p-type ohmic contact layer is superlattice structure composed by a semiconductor layer.

13. The light emitting diode in accordance with claim 4, wherein said p-type cladding layer comprising a doping concentration of magnesium is in a range of from 5×

10¹⁹ to 5×

10²⁰ cm<sup>−

3.</sup>

14. The light emitting diode in accordance with claim 4, wherein said p-type transition layer comprising a doping concentration of magnesium is in a range of from 5×

10¹⁷ to 5×

10¹⁹ cm<sup>−

3</sup>.

15. The light emitting diode in accordance with claim 4, wherein the said p-type ohmic contact layer comprising a doping concentration of magnesium is between said p-type cladding layer and p-type transition layer.

16. The light emitting diode in accordance with claim 11 and 12, wherein said superlattice structure can be stacked by the different compositions, thickness, and doped concentration of semiconductor layer.

17. The light emitting diode in accordance with claim 5, wherein said reflection layer is formed as a Distributed Bragg Reflector which is stacked by semiconductor layer.

18. A manufacturing of light emitting diode comprising the steps of:

providing a substrate; and

forming a semiconductor layer on said substrate to be a light emitting device, wherein said semiconductor layer at least containing a light emitting layer, a p-type semiconductor layer and a n-type semiconductor, and said light emitting layer is between the said n-type semiconductor layer and the p-type semiconductor layer;

wherein forming of said p-type semiconductor comprises the steps of;

forming a p-type cladding layer on said light emitting layer, wherein said p-type cladding layer has an increase of strain in proportion to each layer;

forming a p-type transition layer on said p-type cladding layer; and

forming a p-type ohmic contact layer on said p-type transition layer.

19. The manufacturing method in accordance with claim 18, wherein said p-type cladding layer is doped with magnesium to increase the strain in proportion to each layer.

20. The manufacturing method in accordance with claim 18, wherein the formation of said p-type cladding layer is doped with magnesium to increase the strain in proportion to each layer and then interrupt epitaxial growth and alter the strain of epitaxy layers by controlling the interruption time.

21. The manufacturing method in accordance with claim 18, wherein the formation of said p-type cladding layer is doped with magnesium to increase the strain in proportion to each layer and then interrupt epitaxial growth and alter the strain of epitaxy layers by utilizing the change of temperature.

22. The manufacturing method in accordance with claim 18, wherein the formation of said p-type cladding layer is doped with magnesium to increase the strain in proportion to each layer and then interrupt epitaxial growth and alter the strain of epitaxy layers by forming several monolayers comprising of gallium, indium, or aluminum on the surface of p-type cladding layer.

23. The manufacturing method in accordance with claim 18, wherein the formation of said p-type cladding layer is increasing aluminum composition of p-type cladding layer to raise the strain of epitaxy layers, then interrupt the epitaxial growth and control the interruption time to alter the strain of epitaxy layers.

24. The manufacturing method in accordance with claim 18, wherein the formation of said p-type cladding layer is increasing aluminum composition of p-type cladding layer to raise the strain of epitaxy layers, then interrupt the epitaxial growth and utilize the change of temperature to alter the strain of epitaxy layers.

25. The manufacturing method in accordance with claim 18, wherein the formation of said p-type cladding layer is increasing aluminum composition of p-type cladding layer to raise the strain of epitaxy layers, then interrupt the epitaxial growth and form several monolayers comprising of gallium, indium or aluminum on the surface of p-type cladding layer to alter the strain of epitaxy layers.

26. The manufacturing method in accordance with claim 18, wherein the formation of said p-type transition layer is to control the composition of aluminum among the epitaxy or a dopant of magnesium to reduce the strain in proportion to p-type cladding layer.

27. The manufacturing method in accordance with claim 18, wherein the formation of said p-type transition layer is to reduce the strain between epitaxy layers and p-type cladding layer, next to interrupt epitaxial growth and to control the interruption time to alter the strain of epitaxy layers.

28. The manufacturing method in accordance with claim 18, wherein the formation of said p-type transition layer is to reduce the strain between epitaxy layers and p-type cladding layer, next to interrupt epitaxial growth and to utilize the change of temperature to alter the strain of epitaxy layers.

29. The manufacturing method in accordance with claim 18, wherein the formation of said p-type transition layer is to reduce the strain between epitaxy layers and p-type cladding layer, next to interrupt epitaxial growth and to form several monolayers comprising of gallium, indium or aluminum on the surface of p-type cladding layer to alter the strain of epitaxy layers, wherein the monolayer is from one to five.

33. The manufacturing method in accordance with claim 18, wherein the formation of said p-type ohmic contact layer is utilize epitaxial growth to increase bis(cyclopentadienyl) magnesium (Cp₂Mg) flow or reduce temperature to increase concentration of dopant such as magnesium.

30. The manufacturing method in accordance with 20 or 23 or 27, wherein the interruption time is in a range of from one second to two minutes.

31. The manufacturing method in accordance with 21 or 24 or 28, wherein the change temperature is in a range of from 5°

C. to 300°

C.

32. The manufacturing method in accordance with 22 or 25 or 29, wherein the monolayer in is in a range of from one to five.