Semiconductor device group and method for fabricating the same, and semiconductor device and method for fabricating the same

• US 20050110071A1
• Filed: 10/21/2004
• Published: 05/26/2005
• Est. Priority Date: 10/24/2003
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Kojima, Hideyuki, Anezaki, Toru, Nakagawa, Shinichi, Ema, Taiji
• Granted Patent: US 7,539,963 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor

Abstract

The semiconductor group comprises a first semiconductor device including a first design macro and a nonvolatile memory, and a second semiconductor device including a second design macro having identity with the first design macro and including no nonvolatile memory. The first design macro includes a first active region and a first device isolation region formed on a first semiconductor substrate. The second design macro includes a second active region and a second device isolation region formed on a second semiconductor substrate. A curvature radius of an upper end of the first active region in a cross section is larger than a curvature radius of an upper end of the second active region in a cross section. A difference in height between a surface of the first active region and a surface of the first device isolation region is larger than a difference in height between a surface of the second active region and a surface of the device isolation region.

Claims

1. A semiconductor device group comprising:

a first semiconductor device including a first design macro and a nonvolatile memory, and a second semiconductor device including a second design macro having the identity with the first design macro and including no nonvolatile memory,

the first design macro including a first active region and a first device isolation region formed on a first semiconductor substrate,

the second design macro including a second active region and a second device isolation region formed on a second semiconductor substrate,

a curvature radius of an upper end of the first active region in a cross section being larger than a curvature radius of an upper end of the second active region in a cross section, and

a difference in height between a surface of the first active region and a surface of the first device isolation region being larger than a difference in height between a surface of the second active region and a surface of the second device isolation region.

2. A semiconductor device group according to claim 1, wherein

the curvature radius of the first active region is made larger than the curvature radius of the second active region so that a difference in a characteristic due to the difference in height between the surface of the first active region and the surface of the first device isolation region being different from the difference in height between the surface of the second active region and the surface of the second device isolation region is compensated.

3. A semiconductor device group according to claim 2, wherein

the device characteristic is a channel width dependency of a threshold voltages of a transistor.

4. A semiconductor device group according to claim 1, wherein

the first device isolation region includes a trench formed in the first semiconductor substrate, and an insulating material buried in the trench, and

the second device isolation region includes a trench formed in the second semiconductor substrate, and an insulating material buried in the trench.

5. A semiconductor device group according to claim 1, wherein

the first semiconductor device is an FPGA including the nonvolatile memory, and

the second semiconductor device is an FPGA including no nonvolatile memory.

6. A semiconductor device group according to claim 1, wherein

the first design macro and the second design macro constitute a main logic circuit.

7. A semiconductor device comprising:

a first design macro including a first active region and a first device isolation region formed on a semiconductor substrate; and

a nonvolatile memory,

the semiconductor device constituting a semiconductor device group together with another semiconductor device which comprises a second design macro including a second active region and a second device isolation region formed on another semiconductor substrate and having identity with the first design macro and comprises no nonvolatile memory,

a curvature radius of an upper end of the first active region in a cross section being larger than a curvature radius of an upper end of the second active region in a cross section, and

a difference in height between a surface of the first active region and a surface of the first device isolation region being larger than a difference in height between a surface of the second active region and a surface of the second device isolation region.

8. A semiconductor device comprising:

a first design macro including a first active region and a first device isolation region formed on a semiconductor substrate; and

including no nonvolatile memory,

the semiconductor device constituting a semiconductor device group together with another semiconductor device which comprises a second design macro including a second active region and a second device isolation region formed on another semiconductor substrate and having identity with the first design macro and comprises a nonvolatile memory,

a curvature radius of an upper end of the first active region in a cross section being smaller than a curvature radius of an upper end of the second active region in a cross section, and

a difference in height between a surface of the first active region and a surface of the first device isolation region being smaller than a difference in height between a surface of the second active region and a surface of the second device isolation region.

9. A method for fabricating a semiconductor device group comprising:

a first semiconductor device including a first design macro and a nonvolatile memory; and

a second semiconductor device including a second design macro having identity with the first design macro and including no nonvolatile memory,

the first semiconductor device being fabricated by a semiconductor fabricating method comprising the steps of;

forming a first trench in a first semiconductor substrate;

oxidizing the first semiconductor substrate to round an upper edge of the first trench;

burying a first insulating material in the first trench; and

removing a part of the first insulating material buried in the first trench to from a first recessed region on a surface thereof,

the second semiconductor device being fabricated by a semiconductor fabricating method comprising the steps of;

forming a second trench in the second semiconductor substrate;

oxidizing the second semiconductor substrate to round an upper edge of the second trench;

burying a second insulating material in the second trench; and

removing a part of the second insulating material buried in the second trench to form a second recessed region on a surface thereof,

in the step of rounding the upper edge of the first trench and the step of rounding the upper edge of the second trench, a curvature radius of the upper edge of the first trench being larger than a curvature radius of the upper edge of the second trench, and

in the step of forming the first recessed region and the step of forming the second recessed region, a recess amount of the first recessed region being larger than a recess amount of the second recessed region.

10. A method for fabricating a semiconductor group according to claim 9, wherein

the curvature radius of the first trench is made larger than the curvature radius of the second trench so that a difference in a device characteristic due to a difference between the recess amount of the first recessed region and the recess amount of the second recessed region is compensated.

11. A method for fabricating a semiconductor device group according to claim 10, wherein

the device characteristic is a channel width dependency of a threshold voltage of a transistor.

12. A method for fabricating a semiconductor device group according to claim 9, wherein

an oxidation temperature in the step of rounding the upper edge of the first trench is higher than an oxidation temperature in the step of round the upper edge of the second trench.

13. A semiconductor device comprising:

a first well formed in a first region of a semiconductor substrate;

a second well formed in a second region of the semiconductor substrate;

a device isolation film for defining an active region in the first region and an active region in the second region, the device isolation film having a first step formed on a part corresponding to a bordering edge of the first well;

a first gate insulating film formed on the active region in the first region; and

a second gate insulating film formed on the active region in the second region and being thicker than the first gate insulating film.

15. A semiconductor device according to claim 13, further comprising a third well formed in a third region of the semiconductor substrate,

the device isolation film defining an active region in the third region of the semiconductor substrate and having a second step lower than the first step formed on a part corresponding to a bordering edge of the third well,

further comprising a third gate insulating film formed on the active region in the third region and being thicker than the first gate insulating film and thinner than the second gate insulating film.

17. A semiconductor device according to claim 13, wherein

each of the first well and the second well is a CMOS well including an n-well and a p-well.

19. A semiconductor device according to claim 15, wherein

each of the first well, the second well and the third well is a CMOS well including an n-well and a p-well.

21. A semiconductor device according to claim 13, wherein

the device isolation film has a concavity on a bordering part between the active region and the device isolation film.

14. A semiconductor device comprising:

a first well formed in a first region of a semiconductor substrate;

a second well formed in a second region of the semiconductor substrate;

a device isolation film for defining an active region in the first region and an active region in the second region, the device isolation film having a first step formed on a part corresponding to a bordering edge of the second well;

a first gate insulating film formed in the active region in the first region; and

a second gate insulating film formed in the active region in the second region and being thicker than the first gate insulating film.

16. A semiconductor device according to claim 14, further comprising a third well formed in a third region of the semiconductor substrate,

the device isolation film defining an active region in the third region of the semiconductor substrate and having a second step lower than the first step formed on a part corresponding to a bordering edge of the third well,

further comprising a third gate insulating film formed on the active region in the third region and being thicker than the first gate insulating film and thinner than the second gate insulating film.

18. A semiconductor device according to claim 14, wherein

each of the first well and the second well is a CMOS well including an n-well and a p-well.

20. A semiconductor device according to claim 16, wherein

each of the first well, the second well and the third well is a CMOS well including an n-well and a p-well.

22. A semiconductor device according to claim 14, wherein

the device isolation film has a concavity on a bordering part between the active region and the device isolation film.

23. A method for fabricating a semiconductor device comprising the steps of:

forming a first well in a first region of a semiconductor substrate by using a first mask based on a first mask data;

forming a second well in a second region of the semiconductor substrate by using a second mask based on a second mask data;

growing a first insulating film on the semiconductor substrate;

removing the first insulating film formed in the first region by using a third mask based on the first mask data; and

growing a second insulating film on the semiconductor substrate and on the first insulating film to thereby form a first gate insulating film in the first region and a second gate insulating film thicker than the first gate insulating film in the second region.

24. A method for fabricating a semiconductor device according to claim 23, wherein

in the step of removing a first insulating film, the third mask which is formed based on a first mask data shifted by a certain value is used.

25. A method for fabricating a semiconductor device comprising the steps of:

forming a first well in a first region of a semiconductor substrate by using a first mask based on a first mask data;

forming a second well in a second region of the semiconductor substrate by using a second mask based on a second mask data;

forming a third well in a third region of the semiconductor substrate by using a third mask based on a third mask data;

growing a first insulating film on the semiconductor substrate;

removing the first insulating film formed in the first region and the second region by using a fourth mask based on the first mask data and the second mask data;

growing a second insulating film on the semiconductor substrate and the first insulating film;

removing the second insulating film formed in the first region by using a fifth mask based on the first mask data; and

growing a third insulating film on the semiconductor substrate and the second insulating film to thereby form a first gate insulating film in the first region, a second gate insulating film thicker than the first gate insulating film in the second region and a third gate insulating film thicker than the second insulating film in the third region.

26. A method for fabricating a semiconductor device according to claim 25, wherein

in the step of removing the first insulating film, the fourth mask which is formed based on the first mask data shifted by a certain value and the second mask data shifted by a certain value is used.

27. A method for fabricating a semiconductor device according to claim 25, wherein

in the step of removing the second insulating film, the fifth mask which is formed based on the first mask data shifted by a certain value is used.

28. A method for fabricating a semiconductor device comprising the steps of:

forming a first well in a first region of a semiconductor substrate by using a first mask based on a first mask data;

forming a second well in a second region of the semiconductor substrate by using a second mask based on a second mask data;

growing a first insulating film on the semiconductor substrate;

removing the first insulating film formed in a region other than the second region by using a third mask based on a third mask data prepared by reversing the second mask data;

growing a second insulating film on the semiconductor substrate and the first insulating film to thereby form a first gate insulating film on the first region and a second gate insulating film thicker than the first gate insulating film in the second region.

29. A method for fabricating a semiconductor device according to claim 28, wherein

in the step of removing the first insulating film, the third mask which is formed based on the third mask data shifted by a certain value is used.

30. A method for fabricating a semiconductor device comprising the steps of:

forming a first well in a first region of a semiconductor substrate by using a first mask based on a first mask data;

forming a second well in a second region of the semiconductor substrate by using a second mask based on a second mask data;

forming a third well in a third region of the semiconductor substrate by using a third mask based on a third mask data;

growing a first insulating film on the semiconductor substrate;

removing the first insulating film formed in a region other than the third region by using a fourth mask based on a fourth mask data prepared by reversing the third mask data;

growing a second insulating film on the semiconductor substrate and the first insulating film;

removing the second insulating film formed in a region other than the second region and the third region by using a fifth mask based on the fourth mask data and a fifth mask data prepared by reversing the second mask data; and

growing a third insulating film on the semiconductor substrate and the second insulating film to thereby form a first gate insulating film in the first region, a second gate insulating film thicker than the first gate insulating film in the second region, and a third gate insulating film thicker than the second insulating film in the third region.

31. A method for fabricating a semiconductor device according to claim 30, wherein

in the step of removing the first insulating film, the fourth mask which is formed based on the fourth mask data shifted by a certain value is used.

32. A method for fabricating a semiconductor device according to claim 30, wherein

in the step of removing the second insulating film, the fifth mask which is formed based on the fourth mask data shifted by a certain value and the fifth mask data shifted by a certain value is used.