Circuit arrangement for voltage regulation

• US 20050110477A1
• Filed: 10/05/2004
• Published: 05/26/2005
• Est. Priority Date: 04/05/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mauthe, Manfred
• Granted Patent: US 6,989,660 B2
• Time in Patent Office: Days
• US Class Current: 323/316
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

The invention specifies a circuit arrangement for voltage regulation in which, in addition to a control loop having a comparator (4), an output stage (3) and a feedback path, an auxiliary regulator (11-14) is provided which limits the voltage drop across the output stage (3) and, for this purpose, comprises a control element (11) and a further comparator (13). Hence, the output stage (3) of the voltage regulator may advantageously have a withstand voltage which is lower than the supply voltage which can be supplied at the input (1). On account of its good supply voltage suppression, the voltage regulator described is particularly well suited to supplying on-chip VCOs.

Claims

1. A circuit arrangement for voltage regulation comprising:

an input connection for supplying a supply voltage;

an output connection for tapping off an output voltage;

an output stage comprising a control input and a controlled path having a first and a second load connection, the first load connection being coupled to the input connection, and the second load connection being connected to the output connection and being coupled to a reference potential connection via an electrical load;

a reference generator, which provides the reference potential at its output;

a comparator, which comprises a first input connected to the reference generator a second input coupled to the output connection for regulating the output voltage; and

an auxiliary regulator for limiting the voltage drop across the output stage, comprising a control element that couples the input connection to the controlled path of the output stage at a circuit node and comprising a further comparator having a nominal value input, which is coupled to the control input of the output stage, and having an actual value input, which is coupled to the circuit node.

2. The circuit arrangement of claim 1, further comprising a zero-potential fixed-value voltage source that generates the nominal value.

3. The circuit arrangement of claim 2, wherein the zero-potential fixed-value voltage source is in the form of a floating battery.

4. The circuit arrangement of claim 1, wherein the output stage comprises a MOS transistor.

5. The circuit arrangement of claim 1, wherein the control element in the auxiliary regulator is in the form of a MOS transistor.

6. The circuit arrangement of claim 1, further comprising a voltage divider that couples the output connection to the second input of the comparator.

7. The circuit arrangement of claim 1, wherein the comparator in the circuit arrangement and the further comparator in the auxiliary regulator are respectively in the form of an operational amplifier.

8. The circuit arrangement of claim 1, further comprising a control loop for supplying voltage to the reference generator, said control loop comprising:

a control element having a control input and a controlled path which connects the input connection of the circuit arrangement to an output on the control loop and couples said input connection to a supply connection on the reference generator; and

a comparator having a first input coupled to the output of the reference generator, having a second input coupled to the output of the control element, and having an output which is connected to an input of the reference generator.

9. The circuit arrangement of claim 8, further comprising a changeover switch having a first input connected to the input connection of the circuit arrangement, having a second input connected to the output of the control element, and having an output which is connected to the input of the reference generator.

10. The circuit arrangement of claim 9, further comprising a comparator, having a first input connected to the output of the control element, having a second input connected to the output of the reference generator, and having an output connected to a control input on the changeover switch for the purpose of executing a changeover command.

11. A circuit arrangement for voltage regulation comprising:

an output stage that generates a regulated output voltage;

a control component coupled to the output stage that at least partially controls generation of the regulated output voltage;

a bandgap reference generator coupled to the control component that provides a bandgap voltage; and

an auxiliary regulator coupled to the output stage that limits a voltage drop across the output stage.

12. The circuit arrangement of claim 11, wherein the auxiliary regulator comprises a regulator control component coupled to the output stage that at least partially controls generation of the regulated output voltage.

13. The circuit arrangement of claim 12, wherein the regulator control component further comprises a fixed voltage source coupled to the regulator control component and the output stage.

14. A circuit arrangement for voltage regulation comprising:

an output transistor having a gate connection, a source connection, and a drain connection, wherein the source connection provides a regulated output voltage;

a first differential amplifier having an inverting input, a non-inverting input, and an output, wherein the output is connected to the gate connection of the output transistor;

a bandgap reference generator having a first terminal connected to the non-inverting input of the differential amplifier and a second terminal, wherein a bandgap voltage is supplied to the second terminal;

a voltage divider circuit having a first terminal, a second terminal, and a third terminal, wherein the second terminal generates a fraction of a voltage supplied at the first terminal, wherein the third terminal is connected to the second terminal of the bandgap reference generator, wherein the second terminal is connected to the inverting input of the first differential amplifier; and

wherein the first terminal is connected to the source connection of the output transistor;

a regulating transistor having a gate connection, a source connection, and a drain connection, wherein the source connection receives a supply voltage and wherein the drain connection is connected to a drain connection of the output transistor;

a second differential amplifier having an inverting input, a non-inverting input, and an output, wherein the output is connected to the gate connection of the regulating transistor and wherein the non-inverting input is connected to the drain connection of the regulating transistor; and

a fixed value voltage source having an output terminal and an input terminal and provides an output voltage on the output terminal that is a fixed value above an input voltage on the input terminal, wherein the input terminal is connected to a gate of the output transistor and the output terminal is connected to the inverting input of the second differential amplifier.

15. The circuit arrangement of claim 14, wherein the voltage divider circuit comprises a first resistor across the first and second terminals and a second resistor across the second and third terminals, wherein the first resistor is about 300 ohms and the second resistor is about 1200 ohms.

16. The circuit arrangement of claim 14, wherein the bandgap voltage is about 1.2 volts.

17. The circuit arrangement of claim 14, wherein the regulated output voltage is about 1.5 volts and the supply voltage is about 2.5 volts.

18. The circuit arrangement of claim 14, wherein a withstand voltage of the output transistor is 1.5 volts and a withstand voltage of the regulating transistor is 2.5 volts.

19. The circuit arrangement of claim 14, wherein a withstand voltage of the output transistor less than a withstand voltage of the regulating transistor.

20. The circuit arrangement of claim 14, wherein the output transistor is an NMOS transistor and the regulating transistor is a PMOS transistor.

21. The circuit arrangement of claim 14, further comprising a resistor having a first terminal connected to the source connection of the output transistor and a second terminal connected to the third terminal of the voltage divider circuit and further comprising a capacitor having a first terminal connected to the source connection of the output transistor and a second terminal connected to the third terminal of the voltage divider circuit.