Single supply level converter

• US 20050110519A1
• Filed: 11/24/2003
• Published: 05/26/2005
• Est. Priority Date: 11/24/2003
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Correale, Anthony Jr., Joshi, Rajiv V., Puri, Ruchir, Kung, David S., Pan, Zhigang
• Granted Patent: US 7,119,578 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Claims

1. A level converter for interfacing two circuits supplied by different supply voltages, said level converter comprising:

a first buffer receiving an input signal, said first buffer being connected between a virtual supply and a supply return;

a second buffer receiving an output of said first buffer, connected between a first supply and said supply return; and

a supply select between said first supply and said virtual supply, said supply select receiving an output from said second buffer and selectively passing a first supply voltage on said first supply or a reduced supply voltage to said virtual supply line responsive to said output from said second buffer output.

2. A level converter as in claim 1, wherein said second buffer is an inverter.

3. A level converter as in claim 1, wherein said supply select is a supply switch in parallel with at least one diode, both connected between said first supply and said virtual supply.

4. A level converter as in claim 3, wherein said supply switch is a field effect transistor (FET) gated by said output of said second buffer and said at least one diode is a diode connected FET.

5. A level converter as in claim 4, wherein said supply switch FET is a P-type FET (PFET) and said at least one diode connected FET an N-type FET (NFET) diode.

6. A level converter as in claim 5, wherein said at least one diode connected NFET is a pair of series connected NFET diodes.

7. A level converter as in claim 5, wherein said second buffer is a CMOS inverter.

8. A level converter as in claim 7, wherein said first buffer is a CMOS inverter.

9. A level converter as in claim 7, wherein said first buffer is a logic gate.

10. A level converter as in claim 7, wherein said logic gate is a NAND gate.

11. A level converter as in claim 5, wherein said CMOS inverter includes an NFET having a threshold higher than other NFETs in said level converter.

12. A voltage level converter circuit comprising:

a first inverter with a first inverter input, a first inverter output, a first inverter ground connected to a circuit ground, and a first inverter voltage supply;

a threshold drop element connected between a circuit high voltage supply and the first inverter voltage supply;

a second inverter with a second inverter input connected to the first inverter output, a second inverter output, a second inverter ground connected to the circuit ground, and a second inverter voltage supply connected to the circuit high voltage supply; and

a voltage feedback element connected between the circuit high voltage supply and the first inverter voltage supply, the voltage feedback element having an input connected to the second inverter output, wherein when the second inverter output has a low value, the voltage feedback element causes the first inverter voltage supply to approach the value of the circuit high voltage supply to make the first inverter output high thereby eliminating a standby power in the second inverter.

13. A voltage level converter circuit, as in claim 12, wherein the threshold drop element provides the first inverter voltage supply with a lower voltage than the circuit high voltage supply when the first inverter input is high, whereby standby power is substantially eliminated in the first inverter.

14. A circuit, as in claim 13, wherein the threshold drop element is at least one transistor.

15. A circuit, as in claim 14, wherein the transistor is a field effect transistor (FET).

16. A circuit, as in claim 15, wherein at least one FET is a plurality of FETs.

17. A circuit, as in claim 14, where the FET is a high threshold voltage FET.

18. A circuit, as in claim 13, where the threshold drop element is a diode.

30. An IC as in claim 18, wherein said reduced supply voltage is below V_ddl.

19. An integrated circuit (IC) comprising:

a plurality of circuit rows;

at least one low voltage island in at least one of said plurality of circuit rows, circuit elements in each said at least one low voltage island being powered by a low voltage (V_ddl) supply; and

at least one high voltage island in said at least one of said plurality of circuit rows, circuit elements in each said at least one high voltage island being powered by a high voltage (V_ddh) supply, V_ddh being a higher voltage than V_ddl; and

, at least one level converter comprising;

a first buffer receiving an input signal from said at least one low voltage island, said first buffer being connected between a virtual supply and a supply return;

a second buffer receiving an output of said first buffer and connected between V_ddh and said supply return; and

a supply select between V_ddh and said virtual supply return, said supply select receiving an output from said second buffer and selectively passing V_ddh or a reduced supply voltage to said virtual supply line responsive to said output from said second buffer output.

20. An IC as in claim 19, wherein said second buffer is an inverter.

21. An IC as in claim 19, wherein said supply select is a supply switch in parallel with at least one diode, both connected between said first supply and said virtual supply.

22. An IC converter as in claim 21, wherein said supply switch is a field effect transistor (FET) gated by said output of said second buffer and said at least one diode is a diode connected FET.

23. An IC as in claim 22, wherein said supply switch FET is a P-type FET (PFET) and said at least one diode connected FET an N-type FET (NFET) diode.

24. An IC as in claim 23, wherein said at least one diode connected NFET is a pair of series connected NFET diodes.

25. An IC as in claim 23, wherein said second buffer is a CMOS inverter.

26. An IC as in claim 25, wherein said first buffer is a CMOS inverter.

27. An IC as in claim 25, wherein said first buffer is a logic gate.

28. An IC as in claim 25, wherein said logic gate is a NAND gate receiving a plurality of V_ddl inputs .

29. An IC as in claim 23, wherein said CMOS inverter includes an NFET having a threshold higher than other NFETs in said level converter.