Apparatus and method of processing signals

• US 20050110750A1
• Filed: 11/24/2004
• Published: 05/26/2005
• Est. Priority Date: 11/26/2003
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Dong-Won
• Application Number:
  US10/997,427
• Publication Number:
  US 20050110750A1
• Time in Patent Office: Days
• US Class Current: 345/156
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2340/16 Determination of a pixel data signal depending on the signal applied in the previous frame
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

The signal processing apparatus includes a signal processing portion to receive a first clock and first to third image signals, and generate a second clock, and output corrected image signals with respect to compared results of the first to third image signals; and a frame memory connected to the signal processing portion, and to output the stored first and second image signals to the signal processing portion and to store the third image signals according to the second clock. The signal processing apparatus may reduce costs compared to that of using two or more frame memory and reduce the number of I/O pin of the signal processing apparatus.

Claims

1. A signal processing apparatus, comprising:

a signal processing portion to receive a first clock and first to third image signals, and generate a second clock, and output corrected image signals with respect to compared results of the first to third image signals; and

a frame memory to output the stored first and second image signals to the signal processing portion and to store the third image signals according to the second clock.

2. The signal processing apparatus of claim 1, wherein a frequency of the second clock is higher than that of the first clock.

3. The signal processing apparatus of claim 2, wherein the frame memory stores and outputs the first to third image signals during T/3 period (T:

1 frame).

4. The signal processing apparatus of claim 3, wherein the first to third image signals are image signals during 1 frame period, respectively.

5. The signal processing apparatus of claim 1, wherein the corrected image signals are one of overshoot and undershoot image signals.

6. The signal processing apparatus of claim 2, wherein a frequency of the second clock is 1.5 times as high as that of the first clock.

7. The signal processing apparatus of claim 1, wherein the signal processing portion comprises

a clock generating portion to receive the first clock and to generate the second clock and a third clock;

a first write buffer to store the third image signals according to the third clock, and to output the third image signals according to the second clock;

a second write buffer to store and to output the third image signals according to the third clock; and

first and second read buffers to store the first and second image signals according to the second clock, and to output the first and second image signals according to the third clock.

8. The signal processing apparatus of claim 7, the signal processing portion further comprises a data correction portion to receive the first to third image signals, and to output corrected image signals.

9. The signal processing apparatus of claim 8, wherein a frequency of the third clock is lower than those of the first and second clocks, and a frequency of the second clock is high than that of the first clock.

10. The signal processing apparatus of claim 9, wherein the first write buffer stores the third image signals during T period (T:

1 frame) according to the third clock, and outputs the third image signals during T/3 period according to the second clock.

11. The signal processing apparatus of claim 10, wherein the second write buffer stores the third image signals during T period according to the third clock.

12. The signal processing apparatus of claim 11, wherein the first and second read buffers store the first and second image signals during T/3 period according to the second clock, and output the first and second image signals during T period according to the third clock.

13. The signal processing apparatus of claim 12, wherein a frequency of the second clock is 1.5 times as high as that of the first clock, and a frequency of the third clock is a ½

frequency of the first clock.

14. The signal processing apparatus of claim 13, wherein the first and second read buffers and the first and second write buffers are line memories.

15. The signal processing apparatus of claim 14, wherein the first to third image signals are image signals during 1 frame period.

16. The signal processing apparatus of claim 15, wherein the first write buffer stores the third image signals, and then outputs them after 2T/3 period.

17. The signal processing apparatus of claim 16, wherein the second write buffer stores the third image signals, and then outputs them after T/3 period.

18. The signal processing apparatus of claim 17, wherein the first read buffer stores the first image signals and then outputs them after T/3 period, and the second read buffer stores and outputs them at the same time T/3 period after storing operation of the first read buffer.

19. The signal processing apparatus of claim 18, wherein the first and second read buffers, and the first and second write buffers output the first to third image signals at the same time, respectively.

20. A method of processing signals, comprising:

receiving a first clock and first to third image signals;

generating a second clock according to the first clock;

reading the first and second image signals from a frame memory;

storing the third image signals in the frame memory, and

outputting corrected image signals with respect to compared results of the first to third image signals.

21. The method of claim 20, wherein a frequency of the second clock is higher than that of the first clock.

22. The method of claim 21, wherein the frame memory is performed during T/3 period (T:

1 frame).

23. The method of claim 22, wherein the first to third image signals are image signals during 1 frame period, respectively.

24. The method of claim 20, wherein the corrected image signals are one of overshoot and undershoot image signals.

25. The method of claim 21, wherein the frequency of the second clock is 1.5 times as high as that of the first clock.