OVERLAY AND CD PROCESS WINDOW STRUCTURE

• US 20050110969A1
• Filed: 11/26/2003
• Published: 05/26/2005
• Est. Priority Date: 11/26/2003
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mellinger, Daniel J., Milmore, Timothy C., Nicholls, Matthew C.
• Granted Patent: US 6,967,709 B2
• Time in Patent Office: Days
• US Class Current: 355/53
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70633 Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

The present invention provides photolithographic device and method for optimizing the photolithography process window. The photolithography device comprises a substrate; and a pattern layer having radiant energy transparent portions and radiant energy blocking portions, where the pattern layer has features with a varying overlay. The overlay tolerance is determined by varying the misalignment the features of the pattern. The photolithography device is a reticle. The method for determining an optimum photolithography process window comprises exposing a portion of a wafer to a pattern produced by a reticle, the pattern having a varying overlay that produces multiple photolithography conditions, wherein each photolithography condition has an overlay tolerance; and stepping the reticle across a remaining portion of the wafer, where each step exposes an other region of the wafer to the pattern producing multiple photolithography conditions. This process enables the user to determine the lithographic process window for critical dimension and overlay on a single chip using electrical test structures.

Claims

1. A photolithographic device comprising:

a substrate; and

a pattern layer formed on said substrate including pattern features, said pattern layer having radiant energy transparent portions and radiant energy blocking portions, wherein said pattern features produce a varying overlay when exposed to radiation during a photolithography process.

2. The photolithographic device of claim 1 wherein said varying overlay is produced by pattern features having a varying feature alignment.

3. The photolithography device of claim 2 wherein said varying feature alignment comprises said pattern features misaligned in incremental degrees from a target feature alignment.

4. The photolithographic device of claim 1 wherein said varying overlay is produced by said pattern features having a varying image size.

5. The photolithographic device of claim 4 wherein said varying image size is produced by printing said pattern features having an image size in increasing and decreasing increments from a target dimension.

6. The photolithography device of claim 1 wherein said varying overlay is produced by pattern features having a varying feature alignment and varying image size.

7. The photolithography device of claim 6 wherein said pattern layer comprises a grid of said pattern features having said varying feature alignment and said varying image size, wherein said varying feature alignment comprises incrementally misaligned features from a target feature alignment;

and said varying image size comprises incremental image size variations from a target image dimension.

8. The photolithographic device of claim 1 wherein said pattern layer comprises chromium, chrome oxide, or chromium nitride.

9. A method for determining an optimum photolithography process window comprising:

exposing a portion of a since wafer to a pattern of a reticle, said pattern having pattern features producing varying overlay conditions, wherein each of said varying overlay conditions has a different overlay tolerance contributed by both varying image size and pattern feature alignment built into a reticle design;

stepping said reticle across one or more remaining portions of said single wafer, where each step exposes an other region of said wafer to said reticle pattern features producing said varying overlay conditions;

producing test structures from said varying overlay conditions;

and testing said test structures to determine said optimum photolithography process window.

10. The method according to claim 9 wherein said pattern features further comprise a varying feature alignment and said each of said varying overlay conditions further comprises a feature alignment.

11. The method according to claim 10 wherein said varying feature alignment further comprises said pattern features misaligned in incremental degrees from a target feature alignment.

12. The method according to claim 9 wherein said pattern features further comprise a varying image size, wherein said each overlay condition further comprises an image size.

13. The method according to claim 12 wherein said varying image size further comprises said pattern features dimensioned in increasing and decreasing increments from a target dimension.

22. The method according to claim 9, wherein said optimum photolithography process window takes into account regionality effects of the single wafer.

14. A method for determining an optimum photolithography process window comprising:

exposing a single chip in a wafer to a pattern of a reticle, said pattern having pattern features capable of producing varying overlay conditions, wherein each overlay condition of said varying overlay conditions has a different overlay tolerance contributed by both varying image size and pattern feature alignment built into a reticle design;

producing test structures from said multiple overlay conditions at said single chip; and

testing said test structures, wherein an optimum photolithography process window is determined from exposing a single chip on said wafer.

23. The method according to claim 14, further comprising stepping said reticle across one or more single chip portions of said single wafer, where each step exposes an other region of said wafer to said reticle pattern features producing said varying overlay conditions, wherein said optimum photolithography process window takes into account regionality effects of the single wafer.

15-16. -16. (canceled)

17. A test wafer comprising:

a plurality of test regions; and

a plurality of test structures within each of said plurality of test regions, each of said plurality of test structures having a different alignment between a chain feature and a line feature within each of said test structures, said chain feature and said line feature each in contact with at least one test pad, wherein a total number of test pads within each of said plurality of said test regions is equal to;

a first number of test structures formed by a first photolithography condition multiplied by a first number of test pads required to measure each of said first number of test structures formed by said first photolithography condition; and

one or more other test structures formed by one or more other photolithography conditions multiplied by one or more other number of test pads required to measure each of said one or more other test structures formed by said one or more other photolithography conditions, wherein said first photolithography condition comprises a first alignment between said chain and line feature, and said one or more other photolithography conditions comprises another alignment between said chain and line feature.

18. The test wafer of claim 17 wherein said total number of test pads within each of said plurality of said test regions is equal to:

[(N condition)×

(# test pads for N condition)]+[(N′

condition)×

(# test pads for N′

condition)],

wherein N condition is a first alignment between said chain and said line feature, N′

condition is another alignment between said chain and said line feature, # test pads for N condition equals a number of test pads to test said N condition and # of test pads of N′

condition equals a number of test pads to test said N′

condition.

19. The test wafer of claim 18 wherein said line feature and said chain feature of said plurality of test structures further comprise a different image size

and wherein N condition further comprises a first image size and N′

condition further comprises another image size.

20. The test wafer of claim 19 wherein interaction between said line feature and chain feature is determined from electrical measurements from said plurality of test pads.

21. A test wafer comprising:

a plurality of test regions; and

a plurality of test structures within each of said plurality of test regions, each of said plurality of test structures having a different alignment between a chain feature and a line feature within each of said test structures, said chain feature and said line feature each in contact with at least one test pad, wherein a total number of test pads within each of said plurality of said test regions is equal to;

a first number of test structures formed by a first photolithography condition multiplied by a first number of test pads required to measure each of said first number of test structures formed by said first photolithography condition; and

one or more other test structures formed by one or more other photolithography conditions multiplied by one or more other number of test pads required to measure each of said one or more other test structures formed by said one or more other photolithography conditions, wherein said first photolithography condition comprises a first image size of said chain and line feature, and said one or more other photolithography conditions comprises another image size of said chain and line feature.