Trench power MOSFET with reduced gate resistance

• US 20050112823A1
• Filed: 11/04/2004
• Published: 05/26/2005
• Est. Priority Date: 11/04/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kent, Dave, Montgomery, Robert, Burke, Hugo, Cao, Jianjun, Spring, Kyle, Harvey, Paul
• Granted Patent: US 7,368,353 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof.

Claims

1. A method for manufacturing a power semiconductor device comprising:

forming a mask layer over a first surface of a semiconductor body of a first conductivity;

patterning said mask with a plurality of openings each opening extending to and exposing said first surface of said semiconductor body at the bottom thereof;

defining trenches in said semiconductor body by etching said semiconductor body through said openings, each trench including sidewalls and a bottom;

forming an insulation layer on said sidewalls of said trenches;

forming a gate electrode in each of said trenches, each gate electrode including a free end extending above said first surface into a respective opening in said mask layer; and

removing said mask layer, whereby each gate electrode becomes proud and extends above said first surface of said semiconductor body.

2. A method according to claim 1, wherein said mask layer is comprised of silicon nitride.

3. A method according to claim 1, wherein said gate electrodes are formed by first forming gate electrode material inside said trenches and over said mask layer and then removing gate electrode material the overlies said mask layer.

4. A method according to claim 1, further comprising forming a channel region of a second conductivity in said semiconductor body to a first depth within said semiconductor body, said trenches extending to a depth below said first depth.

5. A method according to claim 1, further comprising siliciding each said gate electrode at its free end prior to removing said mask layer.

6. A method according to claim 5, further comprising forming a region of said first conductivity in said channel region, said region of said first conductivity extending to a depth that is shallower than said first depth.

7. A method according to claim 4, further comprising etching a termination trench in said semiconductor body, said termination trench including a side wall and bottom, extending to a depth below said first depth and defining an active area that includes said trenches.

8. A method according to claim 1, further comprising etching a termination trench in said semiconductor body prior to patterning said mask layer, said termination trench including a side wall and bottom, extending to a depth below said first depth and defining an active area that includes said trenches;

forming a field insulation body over said sidewall and said bottom of said termination trench;

forming an electrically conductive layer over said field insulation and said mask layer; and

etching said electrically conductive layer that overlies said mask layer to define a termination electrode in said termination trench.

9. A method according to claim 8, further comprising siliciding said termination electrode.

10. A method according to claim 1, further comprising forming interlayer insulation over said gate electrode.

11. A method according to claim 10, further comprising forming a channel region of a second conductivity in said semiconductor body, said channel region extending to a first depth;

and forming a region of said first conductivity in said channel region, said region of said first conductivity terminating at a depth shallower than said first depth.

12. A method according to claim 11, wherein said portion of each gate electrode which is proud include sidewalls which terminate at said free end thereof, and further comprising forming insulation spacers along said sidewalls of said proud portion of said gate electrodes, and covering portions of said region of said first conductivity adjacent each gate electrode.

13. A method according to claim 12, further comprising siliciding said free ends of said gate electrodes and said region of said first conductivity not covered by said insulation spacers.

14. A method according to claim 13, further comprising forming an insulation interlayer over said gate electrodes.

15. A method according to claim 14, further comprising forming a metal contact layer in electrical contact with at least said silicide portion of said region of said first conductivity.