METHOD TO FORM FLASH MEMORY WITH VERY NARROW POLYSILICON SPACING

• US 20050112828A1
• Filed: 11/21/2003
• Published: 05/26/2005
• Est. Priority Date: 11/21/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Shih-Chang, Chu, Wen-Ting
• Granted Patent: US 6,924,199 B2
• Time in Patent Office: Days
• US Class Current: 438/296
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new method to form a transistor gate in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A conductor layer is formed overlying the substrate with a dielectric layer therebetween. A masking layer is formed overlying the conductor layer. A resist layer is formed overlying the masking layer. The resist layer is patterned to thereby selectively expose the masking layer. The resist layer exhibits a first spacing between edges of the resist layer. The exposed masking layer is etched through to thereby selectively expose the conductor layer. The etched edges of the masking layer are tapered such that the masking layer exhibits a second spacing between the masking layer edges at the top surface of the conductor layer. The second spacing is less than the first spacing. The exposed conductor layer is etched through to thereby complete a transistor gate.

Claims

1. A method to form a transistor gate in the manufacture of an integrated circuit device, said method comprising:

providing a substrate;

forming a conductor layer overlying said substrate with a dielectric layer therebetween;

forming a masking layer overlying said conductor layer;

forming a resist layer overlying said masking layer;

patterning said resist layer to thereby selectively expose said masking layer wherein said resist layer exhibits a first spacing between edges of said resist layer;

etching through said exposed masking layer to thereby selectively expose said conductor layer wherein etched edges of said masking layer are tapered and the angle of the edges of said masking layer with respect to the top surface of said substrate is between about 45° and

about 85°

such that said masking layer exhibits a second spacing between said masking layer edges at the top surface of said conductor layer and wherein said second spacing is less than said first spacing; and

etching through said exposed conductor layer to thereby complete a transistor gate.

2. The method according to claim 1 wherein said conductor layer comprises polysilicon.

3. The method according to claim 1 wherein said masking layer comprising silicon nitride.

4. The method according to claim 1 wherein said step of etching through said exposed masking layer comprising a dry etch further comprising an etching chemistry of CFH₃, CF₄, O₂, and He.

6. The method according to claim 1 wherein said masking layer comprising a thickness of between about 600 Å

and about 4,000 Å

.

7. The method according to claim 1 further comprising forming an isolation region in said substrate wherein said masking layer etched edges overlies said isolation region.

8. The method according to claim 1 wherein said transistor gate is a floating gate of a non-volatile memory device.

9. The method according to claim 8 further comprising:

forming a control gate overlying said floating gate wherein said control gate comprises a second conductor layer overlying a second dielectric layer; and

forming source and drain regions in said substrate.

5. (canceled)

10. A method to form floating gate of a non-volatile memory device, said method comprising:

providing a substrate;

forming an isolation region in said substrate;

forming a conductor layer overlying said substrate with a dielectric layer therebetween;

forming a masking layer overlying said conductor layer;

forming a resist layer overlying said masking layer;

patterning said resist layer to thereby selectively expose said masking layer wherein said resist layer exhibits a first spacing between edges of said resist layer;

etching through said exposed masking layer to thereby selectively expose said conductor layer wherein etched edges of said masking layer are tapered such that said masking layer exhibits a second spacing between said masking layer edges at the top surface of said conductor layer and wherein said second spacing is less than said first spacing and wherein said masking layer etched edges overlies said isolation region; and

etching through said exposed conductor layer to thereby complete a floating gate of a non-volatile memory device.

11. The method according to claim 10 wherein said conductor layer comprises polysilicon.

12. The method according to claim 10 wherein said masking layer comprising silicon nitride.

13. The method according to claim 10 wherein said step of etching through said exposed masking layer comprising a dry etch further comprising an etching chemistry of CFH₃, CF₄, O₂, and He.

14. The method according to claim 10 wherein the angle of the edges of said masking layer with respect to the top surface of said substrate is between about 45°

and about 85°

.

15. The method according to claim 10 wherein said masking layer comprising a thickness of between about 600 Å

and about 4,000 Å

.

16. The method according to claim 10 further comprising:

forming a control gate overlying said floating gate wherein said control gate comprises a second conductor layer overlying a second dielectric layer; and

forming source and drain regions in said substrate.

17. A method to form floating gate of a non-volatile memory device, said method comprising:

providing a substrate;

forming a shallow trench isolation in said substrate;

forming a polysilicon layer overlying said substrate with a dielectric layer therebetween;

forming a masking layer overlying said polysilicon layer;

forming a resist layer overlying said masking layer;

patterning said resist layer to thereby selectively expose said masking layer wherein said resist layer exhibits a first spacing between edges of said resist layer;

etching through said exposed masking layer to thereby selectively expose said polysilicon layer wherein etched edges of said masking layer are tapered such that said masking layer exhibits a second spacing between said masking layer edges at the top surface of said polysilicon layer and wherein said second spacing is less than said first spacing and wherein said masking layer etched edges overlies said isolation region;

etching through said exposed polysilicon layer to thereby complete a floating gate;

forming a control gate overlying said floating gate wherein said control gate comprises a second conductor layer overlying a second dielectric layer; and

forming source and drain regions in said substrate to complete a non-volatile device.

18. The method according to claim 17 wherein said step of etching through said exposed masking layer comprising a dry etch further comprising an etching chemistry of CFH₃, CF₄, O₂, and He.

19. The method according to claim 17 wherein the angle of the edges of said masking layer with respect to the top surface of said substrate is between 45°

and about 85°

.

20. The method according to claim 17 wherein said masking layer comprising a thickness of between about 600 Å

and about 4,000 Å

.