Method and apparatus for accelerating detection of serial bus device speed signals

• US 20050114582A1
• Filed: 12/21/2004
• Published: 05/26/2005
• Est. Priority Date: 11/16/1999
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Duckwall, William S.
• Granted Patent: US 7,096,302 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

A method and apparatus for accelerating detection of speed code signals, and in particular S400 signals, for IEEE Standard 1394-1995 serial bus devices. The present invention validates S400 mode immediately after detecting an S400 speed signal, or immediately after detecting an S400 speed signal following a first S200 speed signal. The invention further provides S200 and S100 mode validation according to current implementations. Additionally, the invention does not require RX_DATA_PREFIX as a pre-requisite for signal detection.

Claims

1. A method of administering a serial bus, the method comprising the acts of:

receiving a first speed signal by a speed signal register, the first speed signal indicating a first speed code;

receiving a second speed signal by the speed signal register, the second speed signal indicating a second speed code; and

validating a speed mode based on the order in which the speed signals were received.

2. The method of claim 1, wherein the first speed signal is a S200 signal and the second speed signal is an S400 signal, and the speed mode validated is an S400 speed mode.

3. The method of claim 1, wherein the first speed signal is a S200 signal and the second speed signal is a S200 signal, and the speed mode validated is an S200 speed mode.

4. The method of claim 1, wherein the first speed signal is a S200 signal and the second speed signal is an S400 signal, and the speed mode validated is an S400 speed mode.

5. The method of claim 1, further comprising clearing the speed signal register after transmission of a plurality of packets has concluded.

6. The method of claim 1, further comprising clearing the speed signal register after a chip reset has occurred.

7. The method of claim 1, further comprising clearing the speed signal register after a self-ID speed signal trap has occurred.

8. A computer-readable medium containing instructions, which, when executed by a computer, administer a serial bus by:

detecting the receipt of a first speed signal by a speed signal register, the first speed signal indicating a first speed code;

detecting the receipt of a second speed signal by the speed signal register, the second speed signal indicating a second speed code; and

validating a speed mode based on the order in which the speed signals were received.