Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control

• US 20050114850A1
• Filed: 10/18/2004
• Published: 05/26/2005
• Est. Priority Date: 10/29/2003
• Status: Abandoned Application

• Current Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Original Assignee: III Holdings 2, LLC (Intellectual Ventures LLC)
• Inventors: Ashok, Raksit, Chheda, Saurabh, Carver, Kristopher
• Application Number:
  US10/967,989
• Publication Number:
  US 20050114850A1
• Time in Patent Office: Days
• US Class Current: 717/151
• CPC Class Codes: G06F 8/4432 Reducing the energy consumption
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method comprising of analyzing and transforming a program executable at compile-time such that a processor design objective is optimized. A method including analyzing an executable to estimate energy consumption of an application component in a processor. A method including transforming an executable to reduce energy consumption in a processor. A processor framework controlled by compiler inserted control that statically exposes parallelism in an instruction sequence. A processor framework to reduce energy consumption in an instruction memory system with compiler inserted control.

Claims

1. A method, for use in a processor context, comprising of:

analyzing a program executable at compile time;

creating an intermediate program representation of the executable;

analyzing the intermediate representation;

performing a transformation on the intermediate representation such that a design objective is optimized;

generating optimized program executable from the intermediate representation;

2. The method of claim 1, further comprising of transforming an executable to reduce energy consumption in a processor.

3. The method of claim 1, further comprising of transforming an executable to improve performance in a processor.

4. The method of claim 1, further comprising of incorporating information related to energy consumption into an intermediate program representation of an executable.

5. The method of claim 2, wherein an instruction sequence of one or more instructions is replaced with another instruction sequence of one or more instructions to reduce energy.

6. A method, for use in an application or processor context, comprising of:

analyzing a program executable at compile time;

creating an intermediate program representation of the executable;

analyzing the intermediate representation;

estimating energy consumption in a processor for an instruction sequence of one or more instructions in an application.

7. The method of claim 6, further comprising of generating an output to visualize energy consumption in an application component.

8. The method of claim 6, further comprising of identifying an instruction sequence of one or more instructions most likely to contribute significantly to energy consumption.

9. The method of claim 6, further comprising of:

obtaining runtime statistics about an application and its activity in a processor through simulation;

combining simulation information and compile-time information to obtain energy estimations of one or more instructions.

10. A method wherein:

control information is added at compile time related to execution of a sequence of instructions, of one or more instructions, and controlling plural architectural components during execution;

control information related to a sequence of instructions, of one or more instructions, encoded into a processor instruction.

11. The method of claim 10 wherein a control information is inserted targeting energy reduction in a processor.

12. The method of claim 10 wherein control information is encoded into an instruction part of an instruction set architecture.

13. The method of claim 10 wherein control information is encoded into a coprocessor instruction.

14. A processor framework of claim 10 wherein control instructions are inserted for selected instruction sequences and removed at runtime before entering a processor pipeline.

15. The method of claim 10 wherein control information is inserted as program data.

17. A processor framework of claim 10 comprising of a compiler-encoded instruction-level parallelism approach wherein instructions in a sequence of instructions are issued in parallel at runtime on compile-time selected blocks of instructions.

16. A method wherein control information inserted at compile time comprises of:

which instructions in an instruction sequence are to be issued in parallel at runtime;

additional information related to one or more of the following aspects;

which instruction memory structure an instruction sequence should be fetched from,

length of the instruction sequence,

branch prediction mechanism, and

data memory access mechanism.

18. A method of claim 16 wherein coprocessor instructions encode instruction level parallelism.

19. A method, wherein control information is inserted at compile time to determine explicitly which instruction memory structure an instruction sequence should be fetched from.

20. The processor framework of claim 19 comprised of:

one or more Hotblock instruction memory structures exposed to the compiler;

a first level memory structure exposed and controlled by a compiler;

21. An electronics system that implements claim 20.

22. A processor framework of claim 20 where leakage energy reduction is optimized in a memory structure during a time a Hotblock structure is active.