Asymmetric data path media access controller

• US 20050116741A1
• Filed: 12/17/2004
• Published: 06/02/2005
• Est. Priority Date: 09/21/2000
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Tate, Michael
• Granted Patent: US 7,293,123 B2
• Time in Patent Office: Days
• US Class Current: 327/100
• CPC Class Codes: H04L 25/05 Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate

Abstract

A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ones of a first rising edge and a first falling edge of the clock, respectively, to generate two plurality of instances of sampled data having a first width. The plurality of instances of sampled data is then sampled at a second rising edge of the clock and parallelized to generate a second plurality of instances of parallel data having a second width greater than the first width. The parallel data may then be processed to for example generate statistics to monitor link integrity, prior to being transmitted. A 10 Gbps data transmission speed may be maintained using the IEEE 802.3ae-specified media independent interface clock.

Claims

1-36. -36. (canceled)

37. A media access controller, comprising:

a first gate for sampling an input data stream having a first bit width in accordance with a first rising edge of a clock;

a second gate for sampling said input data stream in accordance with a first falling edge of a clock; and

a third gate coupled to said first and second gates for combining outputs of said first and second gates in accordance with a second rising edge of said clock to produce an output data stream having a second bit width greater than said first bit width.

38. The media access controller according to claim 37 further comprising a management control element for processing management control bits in the input data stream to retrieve status information from ISO layers below a MAC layer.

39. The media access controller according to claim 37 further comprising a receive control element coupled to said third gate for providing flow control functionality.

40. The media access controller according to claim 37 further comprising a logic block coupled to the third gate for generating statistics.

41. A media access controller, comprising:

a first data path having a first bit-width; and

a second data path including a receive function element that receives input data at said first bit width and processes said input data to generate output data having a second bit width greater than said first bit width.

42. The media access controller according to claim 41 wherein said receive function element comprises:

a first gate for sampling said input in accordance with a first rising edge of a clock;

a second gate for sampling said input in accordance with a first falling edge of a clock; and

a third gate coupled to said first and second gates for combining outputs of said first and second gates in accordance with a second rising edge of said clock to produce said output data having said second bit width greater than said first bit width.

43. The media access controller according to claim 41 further comprising a management control element for processing management control bits in the input data to retrieve status information from ISO layers below a MAC layer.

44. The media access controller according to claim 42 further comprising a receive control element coupled to said third gate for providing flow control functionality.

45. The media access controller according to claim 42 further comprising a logic block coupled to the third gate for generating statistics.

46-50. -50. (canceled)