Method for operating a memory device

• US 20050117395A1
• Filed: 01/06/2005
• Published: 06/02/2005
• Est. Priority Date: 01/31/2002
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo
• Granted Patent: US 7,190,620 B2
• Time in Patent Office: Days
• US Class Current: 365/185.190
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.

Claims

1. A method for operating bits of memory cells in a memory array, the method comprising:

applying operating pulses to at least one of Type-I bits and Type-II bits of a sample of memory cells, a Type-I bit being defined as a bit in a dual bit cell whose other bit is erased and a Type-II bit being defined as a bit in a dual bit cell whose other bit is programmed;

determining a response of at least one of an electrical, physical and mechanical property of said at least one of Type-I bits and Type-II bits to said operating pulses;

applying at least one operating pulse as a function of said response to at least some other Type-I bits of said array; and

applying at least one further operating pulse as a function of said response to at least some other Type-II bits of said array.

2. The method according to claim 1, wherein said at least one further operating pulse applied to the Type-II bits is greater in at least one of magnitude and duration than the at least one operating pulse applied to other Type-I bits.

3. The method according to claim 1, wherein said at least one further operating pulse applied to the Type-II bits is lower in at least one of magnitude and duration than the at least one operating pulse applied to other Type-I bits.

4. The method according to claim 1, wherein said array comprises memory cells with first-side and second-side bits, and wherein the step of applying at least one operating pulse as a function of said response to at least some other Type-I bits of said array is applied to a first side of the dual bits of the array and said at least one further operating pulse applied to the Type-II bits is applied to the second side of the dual bits of the array.

5. The method according to claim 4, wherein said at least one further operating pulse is applied to all the second side bits that are Type-I bits and which require operating thereon, and all the second side bits that are Type-II bits and which require operating thereon are operated on with at least one further operating pulse different in at least one of magnitude and duration than the operating pulse applied to the first side bits.

6. The method according to claim 4, wherein said at least one further operating pulse is applied to all the second side bits regardless if the second side bits are Type-I or Type-II bits.

7. The method according to claim 6, wherein said at least one further operating pulse is different in at least one of magnitude and duration than the operating pulse applied to the first side bits.

8. The method according to claim 4, wherein said at least one further operating pulse is applied to the second side bits with a different adjustment in at least one of magnitude and duration based on whether the second side bit to be operated on is a Type-I bit or a Type-II bit.

9. The method according to claim 1, wherein applying the at least one operating pulse as a function of said response comprises adjusting the at least one operating pulse with a first adjustment and with a second adjustment as a function of said response, and applying at least one further operating pulse to Type-I bits with the first adjustment and to Type-II bits with the second adjustment.

10. The method according to claim 9, wherein the at least one further operating pulse is applied to the Type-I bits with the first adjustment and only afterwards to Type-II bits with the second adjustment.

11. The method according to claim 9, wherein the at least one further operating pulse is applied to the Type-I bits with the first adjustment and to Type-II bits with the second adjustment in parallel.

12. The method according to claim 1, wherein said array comprises memory cells with two storage areas, wherein all the bits of the memory cells have been erased, and wherein the step of applying at least one operating pulse as a function of said response comprises:

applying programming pulses to not more than one of the two storage areas of each cell, these storage areas including Type-I bits; and

applying programming pulses to the remaining storage areas, regardless if these storage areas are Type-I bits or Type-II bits.