Semiconductor device

• US 20050117433A1
• Filed: 11/23/2004
• Published: 06/02/2005
• Est. Priority Date: 11/27/2003
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Fujisawa, Hiroki
• Granted Patent: US 7,161,865 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A high-density DDR-1/DDR-2 compatible SDRAM chip with a reduced output circuit area is provided. When the SDRAM is a DDR1 SDRAM, an output signal output from an output circuit (14) is output to an output terminal (17) as a main output signal. When the SDRAM is a DDR2 SDRAM, an output signal output from an output circuit (15) is output to the output terminal (17) as the main output signal and, at the same time, the output signal output from the output circuit (14) is output as a sub-output signal to perform operation for adjusting the slew rate or the amount of output current of the main output signal or for adjusting the impedance of the output terminal as viewed from an external point.

Claims

1. A semiconductor device to which one type of power supply selected from at least two different types of power supply voltages is supplied, said semiconductor device comprising:

an output terminal; and

at least two output circuits for said one output terminal

wherein,

said output circuits are configured such that;

when a first power supply voltage is supplied to said semiconductor device, an output signal of a first output circuit is output to said output terminal and

when a second power supply voltage is supplied to said semiconductor device, both the output signal of said first output circuit and an output signal of a second output circuit, which synchronizes with the output signal of said first output circuit, are output to said output terminal.

3. The semiconductor device as defined by claim 1 wherein said first output circuit outputs a main output signal when the first power supply voltage is supplied and said first output circuit outputs a sub-output signal when the second power supply voltage is supplied.

5. The semiconductor device as defined by claim 3 wherein said second output circuit outputs the main output signal when the second power supply voltage is supplied and wherein the sub-output signal is a signal for adjusting the main output signal.

7. The semiconductor device as defined by claim 5 wherein the sub-output signal is a signal for adjusting at least one of a slew rate or an amount of output current of the main output signal or an impedance of said output terminal as viewed from an external point of said output terminal.

9. The semiconductor device as defined by claim 1 wherein, when the second power supply voltage is supplied, said first output circuit comprises a circuit for adjusting a slew rate or an amount of output current of the output signal of said second output circuit or an output impedance of said output terminal as viewed from an external point of said output terminal.

11. The semiconductor device as defined by claim 1 wherein, when the first power supply voltage is supplied, said second output circuit does not output the output signal and, when the second power supply voltage is supplied, outputs a main output signal.

16. The semiconductor device as defined by claim 1 wherein the first power supply voltage is higher than the second power supply voltage.

17. The semiconductor device as defined by claim 1 wherein said semiconductor device is

a double data rate 1 (DDR1) SDRAM when the first power supply voltage is supplied to said semiconductor device and

a double data rate 2 (DDR2) SDRAM when the second power supply voltage is supplied to said semiconductor device.

18. The semiconductor device as defined by claim 1 wherein whether the first power supply voltage or the second power supply voltage is supplied to said semiconductor device is determined by a wiring in said semiconductor device.

19. The semiconductor device as defined by claim 1 wherein said semiconductor device is a synchronous RAM (SDRAM).

2. A semiconductor device to which one type of power supply selected from at least two different types of power supply voltages is supplied, said semiconductor device comprising:

an output terminal; and

at least three output circuits for said one output terminal

wherein,

said output circuits are configured such that;

when a first power supply voltage is supplied to said semiconductor device, both an output signal of a first output circuit and an output signal of a third output circuit, which synchronizes with the output signal of said first output circuit, are output to said output terminal and

when a second power supply voltage is supplied to said semiconductor device, both the output signal of said first output circuit and an output signal of a second output circuit, which synchronizes with the output signal of said first output circuit, are output to said output terminal.

4. The semiconductor device as defined by claim 2 wherein said first output circuit outputs a main output signal when the first power supply voltage is supplied and said first output circuit outputs a sub-output signal when the second power supply voltage is supplied.

6. The semiconductor device as defined by claim 4 wherein said second output circuit outputs the main output signal when the second power supply voltage is supplied and wherein the sub-output signal is a signal for adjusting the main output signal.

8. The semiconductor device as defined by claim 6 wherein the sub-output signal is a signal for adjusting at least one of a slew rate or an amount of output current of the main output signal or an impedance of said output terminal as viewed from an external point of said output terminal.

10. The semiconductor device as defined by claim 2 wherein, when the second power supply voltage is supplied, said first output circuit comprises a circuit for adjusting a slew rate or an amount of output current of the output signal of said second output circuit or an output impedance of said output terminal as viewed from an external point of said output terminal.

12. The semiconductor device as defined by claim 2 wherein, when the first power supply voltage is supplied, said second output circuit does not output the output signal and, when the second power supply voltage is supplied, outputs a main output signal.

13. A semiconductor device to which one type of power supply selected from at least two different types of power supply voltages is supplied, said semiconductor device comprising:

an output terminal;

a first output circuit whose output is connected to said output terminal;

an output signal generation circuit that generates a signal that is a source of a signal output to said output terminal;

a level conversion circuit that converts a voltage level of the signal output from said output signal generation circuit;

a second output circuit that receives the signal output from said output signal generation circuit; and

an adjustment control circuit that generates an adjustment signal from the signal output from said output signal generation circuit

wherein, said semiconductor device is configured such that;

when a first power supply voltage is supplied to said semiconductor device, the output of said level conversion circuit is input to said first output circuit, and

when a second power supply voltage is supplied to said semiconductor device, an output signal of said second output circuit is output to said output terminal and, at the same time, the adjustment signal output from said adjustment control circuit is supplied to said first output circuit to allow an output signal output from said first output circuit to adjust the output signal output from said second output circuit.

14. The semiconductor device as defined by claim 13, further comprising:

a third output circuit that receives the output of said level conversion circuit

wherein, when the first power supply voltage is supplied to said semiconductor device, an output of said third output circuit is supplied to said output terminal.

15. The semiconductor de-vice as defined by claim 13

wherein said first output circuit comprises:

a slew rate adjustment circuit that adjusts a slew rate of the output signal output from said second output circuit;

an output current adjustment circuit that adjusts an amount of current output from said output terminal; and

an output impedance adjustment circuit that adjusts an impedance of said output terminal as viewed from an external point

wherein, when the first power supply voltage is supplied to said semiconductor device, at least one of said slew rate adjustment circuit, said output current adjustment circuit, and said output impedance adjustment circuit receives the output signal converted by said level conversion circuit for driving said output terminal and

wherein, when the second power supply voltage is supplied to said semiconductor device, said slew rate adjustment circuit, said output current adjustment circuit, and said output impedance adjustment circuit drive said output terminal for adjusting the output signal output from said second output circuit.