Semiconductor memory device

• US 20050117434A1
• Filed: 06/28/2004
• Published: 06/02/2005
• Est. Priority Date: 12/01/2003
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Song, Seong-Hwi
• Granted Patent: US 7,151,699 B2
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from being occurred. The semiconductor memory device, which comprises a data inputting block 30 for transferring data applied to a plurality of data input/output pins DQ0 to DQ15 to a plurality of global I/O buses gio<0:15>, a data multiplexing block 32 for multiplexing the data carried on the plurality of global I/O buses gio<0:15> according to a data width option, and a main write driver 34, in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.

Claims

1. A semiconductor memory device, which comprises:

a data inputting means for transferring data applied to a plurality of data input/output pins to a plurality of data buses;

a data multiplexing means for multiplexing the data carried on the plurality of data buses according to a data width option; and

a write driving means, in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.

2. The semiconductor memory device of claim 1, wherein the data multiplexing means includes:

an X16 selecting block for selectively outputting the data carried on the data buses in response to an X16 option selection signal;

an X8 selecting block for selectively outputting eight of the data carried on the data buses in response to an X4/X8 option selection signal X4/X8 and an X8 option selection signal X8; and

an X4 selecting block for selectively outputting four of the 8 data outputted from the X8 selecting block, in response to the X4 option selection signal.

3. The semiconductor memory device of claim 1, wherein the data inputting means includes:

a plurality of data input/output pins;

a plurality of data input buffers for buffering data applied to the plurality of data input/output pins; and

a plurality of pass gates having the output of each of the plurality of data input buffers as its input; and

a data input driver for driving the plurality of data buses with the output of each of the plurality of pass gates.

4. The semiconductor memory device of claim 1, wherein each of the write driving means includes a plurality of write drivers for driving the output signal of the data multiplexing means to a bus in the memory core region, in response to the control signal.

5. The semiconductor memory device of claim 2, wherein the X16 selecting block includes first to sixteen pass gates for selectively passing therethrough the data carried on each of the data buses, in response to the X16 option selection signal X16.

6. The semiconductor memory device of claim 5, wherein the X8 selecting block includes:

1st to 8th NAND gates having the X4/X8 option selection signal and the data carried on different pairs of the data buses as its input, respectively;

1st to 8th inverters having the output signals of the 1st to 8th NAND gates as its input, respectively; and

17th to 24th pass gates having the output signals of the 1st to 8th inverters as its input respectively, and is controlled by the X8 option selection signal.

7. The semiconductor memory device of claim 6, wherein the X4 selecting block includes:

9th to 12th NAND gates having the X4 option selection signal and the output signal of different pairs of the 1st to 8th inverters as its input, respectively;

9th to 12th inverters having the output signals of the 9th to 12th NAND gates as its input, respectively; and

25th to 28th pass gates having the output signals of the 9th to 12th inverters as its input respectively, and is controlled by the X4 option selection signal.