High-definition dual video decoder and decoding method, and digital broadcasting receiver using the same

• US 20050117654A1
• Filed: 11/29/2004
• Published: 06/02/2005
• Est. Priority Date: 11/29/2003
• Status: Abandoned Application

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Im, Jin Seok
• Application Number:
  US10/999,434
• Publication Number:
  US 20050117654A1
• Time in Patent Office: Days
• US Class Current: 375/240.260
• CPC Class Codes: H04N 19/16 for a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/39 involving multiple description coding [MDC], i.e. with separate layers being structured as independently decodable descriptions of input picture data
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/4316 for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/4343 Extraction or processing of packetized elementary streams [PES]
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen

Abstract

A dual video decoder of a digital broadcasting receiver is provided. The decoder includes: a first PES decoder for decoding a first video PES outputted from a first system decoder, into a first video ES; a second PES decoder for decoding a second video PES outputted from a second system decoder, into a second video ES; a VBV (Video Buffer Verifier) buffer memory divided into a first video ES region and a second video ES region; a decoding controller for outputting a control signal to determine a to-be-decoded video ES among the first and second video ESs, and independently decode the first and second video ESs in a single decoding unit; and the single decoding unit for reading the to-be-decoded video ES from the corresponding region of the VBV buffer memory.

Claims

1. A dual video decoder of a digital broadcasting receiver having first and second system decoders for decoding and outputting first and second video PESs (Packetized Elementary Streams) from TS (Transport Stream) bit streams of channels concurrently tuned and demodulated through first and second tuners, the decoder comprising:

a first PES decoder for decoding the first video PES outputted from the first system decoder, into a first video ES;

a second PES decoder for decoding the second video PES outputted from the second system decoder, into a second video ES;

a VBV (Video Buffer Verifier) buffer memory divided into a first video ES region and a second video ES region, for temporarily storing the first and second video ESs outputted from the first and second PES decoders, in corresponding first video ES region and second video ES region;

a decoding controller for, if a decoding mode and a display mode having image information are set, outputting a control signal to determine a to-be-decoded video ES among the first and second video ESs, and independently decode the first and second video ESs in a single decoding unit by using a display synchronous signal; and

the single decoding unit for reading the to-be-decoded video ES from the corresponding region of the VBV buffer memory in a predetermined unit of decoding under the control of the decoding controller to restore the read video ES to an original video signal through VLD (Variable Length Decoding) with synchronization to the display synchronous signal, IQ (Inverse quantizing), IDCT (Inverse Discrete Cosine Transforming), and MC (Motion Compensating).

2. The decoder of claim 1, further comprising a screen combining unit for combining and outputting first and second video signals, which are dual-decoded and outputted in a video frame unit from the single decoding unit, in the display mode.

3. The decoder of claim 1, wherein an input signal of the decoding controller at least has decoding mode information, display mode information, a frame rate and scanning information of a moving picture,

the control signal outputted from the decoding controller to the decoding unit has a decoding mode signal indicating a single video decoding mode or a dual video decoding mode, and identification information (ID) included in the to-be-decoded video ES, and

the display mode information outputted from the decoding controller to a displaying unit at least has a size of a picture to be displayed, a display mode, and memory position information of a video frame.

4. The decoder of claim 1, wherein the video signal of each of the channels tuned through the first and second tuners has a different frame rate or the same frame rate as the display synchronous signal.

5. The decoder of claim 1, wherein each of the video ESs is decoded in a video frame unit in the dual video decoding mode.

6. The decoder of claim 1, wherein the decoding controller controls the frame rate of a corresponding video frame being currently decoded, by using a display field number (display_number), the display field number being the number of the display synchronous signal that allow the displaying of the restored picture.

7. The decoder of claim 6, wherein the decoding controller allocates one of 0, 1, 2 and 3 as the display field number (display_number) depending on the frame rate every display frame of each video bit stream, and reduces a corresponding display field number (display_number) whenever a corresponding decoded video frame is outputted.

8. The decoder of claim 7, wherein the decoding controller outputs the corresponding decoded video frame with the display field number (display_number) of ‘

0’

most prioritized.

9. The decoder of claim 6, wherein if a condition of display_number<

2 is satisfied in the single video decoding mode and a condition of display_number<

3 is satisfied in the dual video decoding mode, the decoding controller controls the single decoding unit to decode the corresponding video frame with synchronization to the display synchronous signal.

10. The decoder of claim 1, wherein the decoding controller allows a parity consistence of a display field of video decoded in the decoding unit, and outputs the decoded video.

11. The decoder of claim 10, wherein a field delay is performed by at least one field for a duration from the decoding to the displaying in the single video decoding mode and is performed by at least one field or two fields for the duration from the decoding to the displaying depending on the frame rate and a decoding synchronous signal duration of each video in the dual video decoding mode, in order to allow the consistence of the display field.

12. The decoder of claim 10, wherein in case where a source of a to-be-decoded video frame is an interlaced scanning, and a to-be-currently-displayed field parity for the to-be-decoded video frame and a field parity of the display synchronous signal is not consistent with each other, the decoding controller suspends the decoding of the to-be-decoded video frame to allow the consistence of the two fields parity.

13. The decoder of claim 1, wherein in case where the display synchronous signal of 30 Hz is used, the decoding controller decodes two video frames of a compression moving picture having frame rates of 59.94 and 60 frames/sec for one display synchronous signal duration in the dual video decoding mode.

14. A dual video decoding method of a digital broadcasting receiver in which first and second video ESs are extracted from video PESs of first and second channels, which are concurrently tuned and demodulated through first and second tuners, and stored in a VBV (Video Buffer Verifier) buffer memory, and the stored first and second video ESs are decoded through a single video decoder, the method comprising the steps of:

(a) if a decoding mode and a display mode having image information are set, determining a to-be-decoded video ES among the first and second video ESs, and waiting a predetermined transition state of a display synchronous signal;

(b) checking the frame rate of the determined to-be-decoded video ES by using a display field number (display_number) determined suitably to the display synchronous signal in a transition state of the display synchronous signal, and performing a next decoding or waiting without the decoding until a next display synchronous signal duration;

(c) decoding picture header information of a corresponding video frame in case where it is determined that a previous decoding is not in a suspended state by using an indication signal informing of suspended decoding, and bypassing the decoding of the picture header information in case where it is determined that the previous decoding is in the suspended state;

(d) comparing a DTS (Decoding Time Stamp), which is inserted into the corresponding video frame, with a STC (System Time Clock), which is calculated by an entire reference clock of the receiver, to determine whether or not to correspond to any one of waiting, skip and decoding states;

(e) in case where it is determined to correspond to the waiting state, setting the indication signal, which informs of the suspended decoding, to ‘

1’

, and waiting without the decoding until the next display synchronous signal duration; and

(f) skipping the decoding of the determined to-be-decoded video ES in a predetermined unit of decoding in case where it is determined to correspond to the skip state, and performing the determined to-be-decoded video ES in a video frame unit in case where it is determined to correspond to the decoding state.

15. The method of claim 14, wherein in the (b) step, the next decoding is performed to synchronize the corresponding video frame to the display synchronous signal to decode the synchronized corresponding video frame in case where a condition of display_number<

2 is satisfied in a single video decoding mode and a condition of display_number<

3 is satisfied in a dual video decoding mode, and waiting without the decoding until the next display synchronous signal duration in case where the conditions are not satisfied.

16. The method of claim 14, the (f) step comprises the steps of:

in case where it is determined that the inputted source is an interlaced scanning moving picture while being in the decoding state in the (d) step, checking whether or not a to-be-currently-displayed field parity for each video bit stream and a field parity of the display synchronous signal is consistent with each other; and

only in case where it is determined that two fields parity is consistent, decoding the corresponding video frame, and in case where it is determined that they is not consistent, setting the indication signal to ‘

1’ and

suspending the decoding until the next display synchronous signal duration.

17. The method of claim 14, wherein in case where the display synchronous signal of 30 Hz is used, the decoding controller decodes two video frames of a compression moving picture having frame rates of 59.94 and 60 frames/sec for one display synchronous signal duration in the dual video decoding mode.

18. The method of claim 14, wherein the (a) step further comprises a step of waiting until the next display synchronous signal duration if the video ES sufficient for decoding is not stored in the VBV buffer memory.

19. A digital broadcasting receiver comprising:

a first tuner for tuning one of a plurality of channel signals received through an antenna, to demodulate the tuned channel signal to a first TS (Transport Stream) bit stream;

a second tuner for tuning one of the plurality of channel signals received through the antenna, to demodulate the tuned channel signal to a second TS bit stream;

a first system decoder for decoding a first video PES from the demodulated first TS bit steam, and outputting the decoded first video PES;

a second system decoder for decoding a second video PES from the demodulated second TS bit steam, and outputting the decoded second video PES;

a single video decoder for decoding each of the first and second video PESs outputted from the first and second system decoders into the video ESs, and determining a to-be-decoded video ES among the first and second video ESs depending on the decoding mode and the display mode, and decoding the determined to-be-decoded video ES in a video frame unit at a predetermined transition state of a display synchronous signal; and

a screen combining unit for combining and outputting first and second video signals, which are dual-decoded and outputted in the video frame unit from the single video decoder, in the display mode.

20. The receiver of claim 19, wherein the single video decoder comprises:

a first PES decoder for decoding the first video PES outputted from the first system decoder, into the first video ES;

a second PES decoder for decoding the second video PES outputted from the second system decoder, into the second video ES;

a VBV (Video Buffer Verifier) buffer memory divided into a first video ES region and a second video ES region, for temporarily storing the first and second video ESs outputted from the first and second PES decoders, in corresponding first video ES region and second video ES region;

a decoding controller for, if the decoding mode and the display mode having image information are set, outputting a control signal to determine the to-be-decoded video ES among the first and second video ESs, and independently decode the first and second video ESs in a decoding unit by using the display synchronous signal; and

the decoding unit for reading the to-be-decoded video ES from the corresponding region of the VBV buffer memory in a predetermined unit of decoding under the control of the decoding controller to restore the read video ES to an original video signal through VLD (Variable Length Decoding) with synchronization to the display synchronous signal, IQ (Inverse quantizing), IDCT (Inverse Discrete Cosine Transforming), and MC (Motion Compensating)

21. The receiver of claim 20, wherein the decoding controller controls to wait until a next display synchronous signal duration if the video ES sufficient for decoding is not stored in the VBV buffer memory.

22. The receiver of claim 19, wherein the decoding controller controls to check whether or not a to-be-currently-displayed field parity for each video bit stream and a field parity of the display synchronous signal is consistent, and if it is determined that they is not consistent, the decoding controller controls to suspend the decoding until the next display synchronous signal duration.